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https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
ddr_tool: some error need fix [1/1]
PD#SWPL-123454 Problem: some error need fix Solution: dmc show include mode ddr banwidth device port set error ddr priority fix Verify: local Change-Id: If7d3034c9e18562b42d8ca235c79566f5c18147a Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
This commit is contained in:
committed by
gerrit autosubmit
parent
7b60e2243c
commit
ae17aa4b79
@@ -44,7 +44,7 @@ static void g12_dmc_port_config(struct ddr_bandwidth *db, int channel, int port)
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val = 0xffff;
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writel(val, db->ddr_reg1 + rs[channel]);
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} else {
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val = (0x1 << 23); /* select device */
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val = (0x1 << 7); /* select device */
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writel(val, db->ddr_reg1 + rp[channel]);
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val = readl(db->ddr_reg1 + rs[channel]);
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val |= (1 << subport);
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@@ -92,7 +92,7 @@ static void s4_dmc_port_config(struct ddr_bandwidth *db, int channel, int port)
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val = 0xffff;
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writel(val, db->ddr_reg1 + off + 8); /* DMC_MON*_CTRL2 */
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} else {
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val = (0x1 << 23); /* select device */
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val = (0x1 << 7); /* select device */
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writel(val, db->ddr_reg1 + off + 4);
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val = readl(db->ddr_reg1 + off + 8);
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val |= (1 << subport);
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@@ -92,7 +92,7 @@ static void t5_dmc_port_config(struct ddr_bandwidth *db, int channel, int port)
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val = 0xffff;
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writel(val, db->ddr_reg1 + off + 8); /* DMC_MON*_CTRL2 */
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} else {
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val = (0x1 << 23); /* select device */
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val = (0x1 << 7); /* select device */
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writel(val, db->ddr_reg1 + off + 4);
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val = readl(db->ddr_reg1 + off + 8);
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val |= (1 << subport);
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@@ -76,6 +76,13 @@ static int dmc_dev_is_byte(struct ddr_bandwidth *db)
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return 0;
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}
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static int ddr_width_is_16bit(struct ddr_bandwidth *db)
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{
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if (db && (db->soc_feature & DDR_WIDTH_IS_16BIT))
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return 1;
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return 0;
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}
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static int dmc_is_asymmetry(struct ddr_bandwidth *db)
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{
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if (db && (db->soc_feature & DMC_ASYMMETRY))
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@@ -199,7 +206,7 @@ static void cal_ddr_usage(struct ddr_bandwidth *db, struct ddr_grant *dg)
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* After s4 soc, not register to distinguish ddr data bus width,
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* default ereryone dmc bus width is 32, but p1 and s5 is 16.
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*/
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if (db->cpu_type == DMC_TYPE_P1 || db->cpu_type == DMC_TYPE_S5)
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if (ddr_width_is_16bit(db))
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mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number / 2;
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else
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mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number;
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@@ -445,7 +452,7 @@ static ssize_t port_store(struct class *cla,
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if (port < 0) /* clear port set */
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aml_db->port[ch] = 0;
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else
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aml_db->port[ch] |= 1ULL << (port & 0x1f);
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aml_db->port[ch] |= 1ULL << (port & 0x3f);
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aml_db->ops->config_port(aml_db, ch, port);
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}
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}
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@@ -1216,6 +1223,7 @@ static int __init init_chip_config(int cpu, struct ddr_bandwidth *band)
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band->channels = 8;
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band->dmc_number = 4;
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band->soc_feature |= DMC_DEVICE_8BIT;
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band->soc_feature |= DDR_WIDTH_IS_16BIT;
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band->mali_port[0] = 3; /* port3: mali */
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band->mali_port[1] = 4;
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break;
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@@ -1264,6 +1272,7 @@ static int __init init_chip_config(int cpu, struct ddr_bandwidth *band)
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band->channels = 8;
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band->dmc_number = 4;
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band->soc_feature |= DMC_DEVICE_8BIT;
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band->soc_feature |= DDR_WIDTH_IS_16BIT;
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band->mali_port[0] = 4;
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band->mali_port[1] = -1;
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break;
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@@ -20,7 +20,8 @@
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#define MAX_DMC_NUM 4
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/* for soc_feature */
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#define DMC_ASYMMETRY BIT(3)
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#define DMC_ASYMMETRY BIT(4)
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#define DDR_WIDTH_IS_16BIT BIT(3)
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#define DMC_DEVICE_8BIT BIT(2)
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#define PLL_IS_SEC BIT(1)
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@@ -15,6 +15,8 @@
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#include "ddr_port.h"
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#include "ddr_bandwidth.h"
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#define PRIORITY_NUM (aml_db->ddr_priority_num & 0xffff)
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static struct ddr_priority ddr_priority_s4[] __initdata = {
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{ .port_id = 0, .reg_base = 0xfe036000,
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.reg_mode = 0, .reg_config = 0,
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@@ -797,7 +799,7 @@ static int ddr_priority_get_info(unsigned char port_id)
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return -EINVAL;
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}
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for (i = 0; i < aml_db->ddr_priority_num; i++) {
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for (i = 0; i < PRIORITY_NUM; i++) {
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if (aml_db->ddr_priority_desc[i].port_id == port_id)
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return i;
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}
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@@ -974,7 +976,7 @@ int priority_display(char *buf)
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"\tparm2: 'r' or 'w' priority (default set all)\n");
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s += sprintf(buf + s, "\tid\t name \t\tw_current \tw_max \t\tr_current \tr_max\n");
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for (i = 0; i < aml_db->ddr_priority_num; i++) {
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for (i = 0; i < PRIORITY_NUM; i++) {
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info = aml_db->ddr_priority_desc[i];
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ret = ddr_priority_rw(info.port_id, &priority_r, &priority_w, DMC_READ);
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@@ -374,7 +374,8 @@ size_t dump_dmc_reg(char *buf)
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sz += sprintf(buf + sz, "IO_BASE:%lx\n", dmc_mon->io_base);
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sz += sprintf(buf + sz, "RANGE:%lx - %lx\n",
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dmc_mon->addr_start, dmc_mon->addr_end);
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sz += sprintf(buf + sz, "MONITOR DEVICE:\n");
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sz += sprintf(buf + sz, "MONITOR DEVICE(%s):\n",
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dmc_mon->configs & POLICY_INCLUDE ? "include" : "exclude");
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if (!dmc_mon->device)
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return sz;
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@@ -719,6 +720,7 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon)
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/* set default parameters */
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mon->debug = 0x01;
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mon->mon_number = 1;
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mon->configs |= POLICY_INCLUDE;
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switch (chip) {
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#ifdef CONFIG_AMLOGIC_DMC_MONITOR_G12
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@@ -780,13 +782,11 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon)
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case DMC_TYPE_T7:
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case DMC_TYPE_T3:
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mon->ops = &t7_dmc_mon_ops;
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mon->configs |= POLICY_INCLUDE;
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mon->configs |= DMC_DEVICE_8BIT;
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mon->mon_number = 2;
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break;
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case DMC_TYPE_P1:
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mon->ops = &t7_dmc_mon_ops;
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mon->configs |= POLICY_INCLUDE;
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mon->configs |= DMC_DEVICE_8BIT;
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mon->mon_number = 4;
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break;
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@@ -800,14 +800,12 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon)
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#ifdef CONFIG_AMLOGIC_DMC_MONITOR_C3
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case DMC_TYPE_C3:
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mon->ops = &c3_dmc_mon_ops;
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mon->configs |= POLICY_INCLUDE;
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mon->configs |= DMC_DEVICE_8BIT;
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break;
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#endif
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#ifdef CONFIG_AMLOGIC_DMC_MONITOR_T5M
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case DMC_TYPE_T5M:
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mon->ops = &t5m_dmc_mon_ops;
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mon->configs |= POLICY_INCLUDE;
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mon->configs |= DMC_DEVICE_8BIT;
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mon->mon_number = 2;
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break;
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@@ -815,13 +813,11 @@ static void __init get_dmc_ops(int chip, struct dmc_monitor *mon)
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#ifdef CONFIG_AMLOGIC_DMC_MONITOR_S5
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case DMC_TYPE_S5:
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mon->ops = &s5_dmc_mon_ops;
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mon->configs |= POLICY_INCLUDE;
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mon->configs |= DMC_DEVICE_8BIT;
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mon->mon_number = 4;
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break;
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case DMC_TYPE_T3X:
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mon->ops = &s5_dmc_mon_ops;
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mon->configs |= POLICY_INCLUDE;
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mon->configs |= DMC_DEVICE_8BIT;
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mon->mon_number = 2;
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break;
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