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drm: fix reset of mif reg VIU_OSD2_CTRL_STAT [1/1]

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PD#SWPL-168643

Problem:
osd_cfg_sync_en bit of mif reg VIU_OSD2_CTRL_STAT gets
reset to be 1 after resuming.

Solution:
set osd_cfg_sync_en bit to be 0 in each commit if 1.

Verify:
s7

Test:
DRM-OSD-70

Change-Id: I7d3885eab088a597c25b41e0ce4b4377482315ba
Signed-off-by: yujun.zhang <yujun.zhang@amlogic.com>
This commit is contained in:
yujun.zhang
2024-06-28 15:09:46 +08:00
committed by Luan Yuan
parent 8b9ce68999
commit beb86f028a
1 changed files with 14 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/drm/vpu-hw/meson_vpu_osd_mif.c
+14
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@@ -1114,6 +1114,20 @@ void osd_ctrl_init(struct meson_vpu_block *vblk, struct rdma_reg_ops *reg_ops,
/*Need config follow crtc index.*/
u8 holdline = VIU1_DEFAULT_HOLD_LINE;
u8 fifo_val = 0x20;
u32 osd_cfg_sync_en = 0;
/* S7 and t5w are platforms with low-power consumption, so resuming will
* cause osd_cfg_sync_en bit of viu_osd_ctrl_stat to reset to be 1, not initial 0
* anymore.Other previous platforms would not reset and always keep it to be initial 0.
* Currently, 0 is configured anyway to fix it.
* TODO: reset callback for each block is needed for more complicated reset cases.
*/
osd_cfg_sync_en = meson_drm_read_reg(reg->viu_osd_ctrl_stat) & 0x80000000;
osd_cfg_sync_en = osd_cfg_sync_en >> 31;
if (osd_cfg_sync_en == 1) {
reg_ops->rdma_write_reg_bits(reg->viu_osd_ctrl_stat, 0, 31, 1);
MESON_DRM_BLOCK("fixed reset of osd_cfg_sync_en in mif [%d].\n", vblk->index);
}
if (vblk->init_done)
return;