yujun.zhang beb86f028a drm: fix reset of mif reg VIU_OSD2_CTRL_STAT [1/1] ...

PD#SWPL-168643

Problem:
osd_cfg_sync_en bit of mif reg VIU_OSD2_CTRL_STAT gets
reset to be 1 after resuming.

Solution:
set osd_cfg_sync_en bit to be 0 in each commit if 1.

Verify:
s7

Test:
DRM-OSD-70

Change-Id: I7d3885eab088a597c25b41e0ce4b4377482315ba
Signed-off-by: yujun.zhang <yujun.zhang@amlogic.com>

2024-07-18 13:38:06 +08:00

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auto_patch

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drivers

drm: fix reset of mif reg VIU_OSD2_CTRL_STAT [1/1]

2024-07-18 13:38:06 +08:00

include

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