mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
tvafe: change avin detected config [1/1]
PD#SWPL-138917 Problem: avin detected config need optimize Solution: change avin detected config Verify: txhd2 Change-Id: I7548bf0ca33df5d11d7096d0c7f02285317d4798 Signed-off-by: qiang.liu <qiang.liu@amlogic.com>
This commit is contained in:
@@ -72,8 +72,6 @@ static unsigned int trigger_sel = 1;
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static unsigned int irq_edge_en = 1;
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static unsigned int irq_filter;
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static unsigned int irq_pol;
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static unsigned int avin_count_times = 5;
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@@ -497,7 +495,7 @@ static void tvafe_avin_detect_anlog_config(void)
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W_HIU_BIT(meson_data->detect_cntl, 1,
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AFE_T5_CH2_EN_DC_BIAS_BIT,
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AFE_T5_CH2_EN_DC_BIAS_WIDTH);
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W_HIU_BIT(HHI_CVBS_DETECT_CNTL, meson_data->vdc_level,
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W_HIU_BIT(meson_data->detect_cntl, meson_data->vdc_level,
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AFE_DETECT_RSV_BIT, AFE_DETECT_RSV_WIDTH);
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} else {
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/*ch config*/
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@@ -556,27 +554,37 @@ static void tvafe_avin_detect_anlog_config(void)
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static void tvafe_avin_detect_digital_config(void)
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{
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if (!meson_data) {
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tvafe_pr_info("%s: meson_data is null\n", __func__);
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int i;
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unsigned int device_mask;
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unsigned int irq_cntl;
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if (!meson_data || !av_dev) {
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tvafe_pr_info("%s: meson_data or av_dev is null\n", __func__);
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return;
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}
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tvafe_avin_irq_update_bit(meson_data->irq0_cntl,
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CVBS_IRQ_MODE_MASK << CVBS_IRQ_MODE_BIT,
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irq_mode << CVBS_IRQ_MODE_BIT);
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device_mask = av_dev->dts_param.device_mask;
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irq_cntl = meson_data->irq0_cntl;
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for (i = 0; i < TVAFE_MAX_AVIN_DEVICE_NUM && (device_mask & BIT(0)); i++) {
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tvafe_avin_irq_update_bit(irq_cntl,
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CVBS_IRQ_MODE_MASK << CVBS_IRQ_MODE_BIT,
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irq_mode << CVBS_IRQ_MODE_BIT);
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tvafe_avin_irq_update_bit(irq_cntl,
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CVBS_IRQ_TRIGGER_SEL_MASK << CVBS_IRQ_TRIGGER_SEL_BIT,
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trigger_sel << CVBS_IRQ_TRIGGER_SEL_BIT);
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tvafe_avin_irq_update_bit(irq_cntl,
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CVBS_IRQ_EDGE_EN_MASK << CVBS_IRQ_EDGE_EN_BIT,
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irq_edge_en << CVBS_IRQ_EDGE_EN_BIT);
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tvafe_avin_irq_update_bit(irq_cntl,
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CVBS_IRQ_FILTER_MASK << CVBS_IRQ_FILTER_BIT,
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meson_data->irq_filter << CVBS_IRQ_FILTER_BIT);
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tvafe_avin_irq_update_bit(irq_cntl,
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CVBS_IRQ_POL_MASK << CVBS_IRQ_POL_BIT,
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irq_pol << CVBS_IRQ_POL_BIT);
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tvafe_avin_irq_update_bit(meson_data->irq0_cntl,
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CVBS_IRQ_TRIGGER_SEL_MASK << CVBS_IRQ_TRIGGER_SEL_BIT,
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trigger_sel << CVBS_IRQ_TRIGGER_SEL_BIT);
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tvafe_avin_irq_update_bit(meson_data->irq0_cntl,
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CVBS_IRQ_EDGE_EN_MASK << CVBS_IRQ_EDGE_EN_BIT,
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irq_edge_en << CVBS_IRQ_EDGE_EN_BIT);
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tvafe_avin_irq_update_bit(meson_data->irq0_cntl,
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CVBS_IRQ_FILTER_MASK << CVBS_IRQ_FILTER_BIT,
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irq_filter << CVBS_IRQ_FILTER_BIT);
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tvafe_avin_irq_update_bit(meson_data->irq0_cntl,
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CVBS_IRQ_POL_MASK << CVBS_IRQ_POL_BIT,
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irq_pol << CVBS_IRQ_POL_BIT);
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device_mask >>= 1;
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irq_cntl = meson_data->irq1_cntl;
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}
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}
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static int tvafe_avin_open(struct inode *inode, struct file *file)
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@@ -714,7 +722,7 @@ static void tvafe_avin_detect_state(struct tvafe_avin_det_s *av_dev)
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tvafe_pr_info("irq_mode: %d\n", irq_mode);
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tvafe_pr_info("trigger_sel: %d\n", trigger_sel);
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tvafe_pr_info("irq_edge_en: %d\n", irq_edge_en);
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tvafe_pr_info("irq_filter: %d\n", irq_filter);
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tvafe_pr_info("irq_filter: %d\n", meson_data->irq_filter);
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tvafe_pr_info("irq_pol: %d\n", irq_pol);
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}
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@@ -908,14 +916,14 @@ static ssize_t debug_store(struct device *dev,
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__func__, irq_edge_en);
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} else if (!strcmp(parm[0], "irq_filter")) {
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if (parm[1]) {
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if (kstrtouint(parm[1], 10, &irq_filter)) {
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if (kstrtouint(parm[1], 10, &meson_data->irq_filter)) {
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tvafe_pr_info("[%s]:invalid parameter\n",
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__func__);
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goto tvafe_avin_detect_store_err;
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}
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}
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tvafe_pr_info("[%s]: irq_filter: %d\n",
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__func__, irq_filter);
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__func__, meson_data->irq_filter);
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} else if (!strcmp(parm[0], "irq_pol")) {
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if (parm[1]) {
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if (kstrtouint(parm[1], 10, &irq_pol)) {
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@@ -1034,7 +1042,7 @@ static void tvafe_avin_detect_timer_handler(struct timer_list *avin_detect_timer
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goto TIMER;
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}
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} else if (av_dev->dts_param.device_mask == TVAFE_AVIN_CH2_MASK) {
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av_dev->irq_counter[0] = aml_read_cbus(meson_data->irq1_cnt);
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av_dev->irq_counter[0] = tvafe_avin_irq_reg_read(meson_data->irq1_cnt);
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if (meson_data) {
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if (!R_HIU_BIT(meson_data->detect_cntl,
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AFE_TL_CH2_EN_DETECT_BIT, AFE_TL_CH2_EN_DETECT_WIDTH))
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@@ -1045,8 +1053,8 @@ static void tvafe_avin_detect_timer_handler(struct timer_list *avin_detect_timer
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goto TIMER;
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}
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} else if (av_dev->dts_param.device_mask == TVAFE_AVIN_MASK) {
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av_dev->irq_counter[0] = aml_read_cbus(meson_data->irq0_cnt);
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av_dev->irq_counter[1] = aml_read_cbus(meson_data->irq1_cnt);
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av_dev->irq_counter[0] = tvafe_avin_irq_reg_read(meson_data->irq0_cnt);
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av_dev->irq_counter[1] = tvafe_avin_irq_reg_read(meson_data->irq1_cnt);
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if (meson_data) {
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if (!R_HIU_BIT(meson_data->detect_cntl,
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AFE_CH1_EN_DETECT_BIT, AFE_CH1_EN_DETECT_WIDTH) ||
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@@ -1449,9 +1457,10 @@ struct meson_avin_data txhd2_data = {
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.irq1_cntl = CVBS_IRQ1_CNTL,
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.irq0_cnt = CVBS_IRQ0_COUNTER,
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.irq1_cnt = CVBS_IRQ1_COUNTER,
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.dc_level_adj = 3,
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.dc_level_adj = 2,
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.vdc_level = 3,
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.comp_level_adj = 3,
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.irq_filter = 1,
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};
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static const struct of_device_id tvafe_avin_dt_match[] = {
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@@ -167,6 +167,7 @@ struct meson_avin_data {
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unsigned int vdc_level;
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/*0:635mv; 1:686mv; 2:733mv; 3:776mv; 4:816mv; 5:853mv; 6:887mv; 7:919mv*/
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unsigned int comp_level_adj;
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unsigned int irq_filter;
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};
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void tvafe_cha1_SYNCTIP_close_config(void);
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@@ -837,8 +837,10 @@ static void tvafe_cvd2_info_init(struct tvafe_cvd2_s *cvd2)
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inline void tvafe_cvd2_try_format(struct tvafe_cvd2_s *cvd2,
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struct tvafe_cvd2_mem_s *mem, enum tvin_sig_fmt_e fmt)
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{
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if (always_try_format)
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if (always_try_format) {
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fmt = always_try_format;
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cvd2->manual_fmt = always_try_format;
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}
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/* check format validation */
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if (fmt < TVIN_SIG_FMT_CVBS_NTSC_M ||
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@@ -4249,8 +4249,10 @@ bool vdin_check_cycle(struct vdin_dev_s *devp)
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/* TODO:whether T5/TL1/TXHD2/T3X support cycle check */
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if (!(is_meson_t7_cpu() || is_meson_t3_cpu() ||
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is_meson_t5w_cpu() || is_meson_t5m_cpu()) &&
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interval_value > VDIN_INPUT_MAX_FPS)
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interval_value > VDIN_INPUT_MAX_FPS) {
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devp->stats.cycle_err_cnt_con = 0;
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return false;
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}
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/* if continuous cycle error over 10 times,call hdmi_clr_vsync to recovery */
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if (devp->frontend)
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