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https://github.com/hardkernel/kernel_common_drivers.git
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dts: drm multi-display in 5.15 [1/1]
PD#SWPL-94676 Problem: No dts config in kernel 5.15 Solution: Add dts config for multiple DRM display Verify: t7c Change-Id: Ia418eabbb2a6fa366bd796977fc8bfcca88cf76b Signed-off-by: yujun.zhang <yujun.zhang@amlogic.com>
This commit is contained in:
yujun.zhang
committed by
Qianggui Song
Qianggui Song
parent
ffad82952a
commit
dd2125bb0e
@@ -0,0 +1,302 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/display/meson-drm-ids.h>
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#include "mesont7c.dtsi"
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/ {
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drm_amcvbsout: drm-amcvbsout {
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status = "disabled";
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compatible = "amlogic, drm-cvbsout";
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dev_name = "meson-amcvbsout";
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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cvbs_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_cvbs>;
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};
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};
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};
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};
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drm_vpu: drm-vpu@0xff900000 {
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status = "disabled";
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compatible = "amlogic, meson-t7-vpu";
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osd_ver = /bits/ 8 <OSD_V7>;
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reg = <0x0 0xff900000 0x0 0x40000>,
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<0x0 0xff63c000 0x0 0x2000>,
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<0x0 0xff638000 0x0 0x2000>;
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reg-names = "base", "hhi", "dmc";
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "drm-viu-vsync", "drm-viu2-vsync",
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"drm-viu3-vsync";
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clocks = <&clkc CLKID_VPU_CLKC_MUX>;
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clock-names = "vpu_clkc";
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dma-coherent;
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/*EXTERNAL port for driver outside of drm.*/
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connectors_dev: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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drm_to_hdmitx: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&hdmitx_to_drm>;
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};
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drm_to_cvbs: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&cvbs_to_drm>;
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};
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drm_to_lcd0: endpoint@2 {
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reg = <2>;
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remote-endpoint = <0>;
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};
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drm_to_lcd1: endpoint@3 {
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reg = <3>;
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remote-endpoint = <0>;
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};
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drm_to_lcd2: endpoint@4 {
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reg = <4>;
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remote-endpoint = <0>;
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};
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};
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};
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drm_subsystem: drm-subsystem {
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status = "okay";
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compatible = "amlogic, drm-subsystem";
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ports = <&connectors_dev>;
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fbdev_sizes = <1920 1080 1920 2160 32>;
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osd_ver = /bits/ 8 <OSD_V7>;
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vfm_mode = <1>; /** 0:drm mode 1:composer mode */
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memory-region = <&logo_reserved>;
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crtc_masks = <7 7 1>; /*for encoder: 0:hdmi 1:lcd 2:cvbs*/
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crtcmask_of_osd = <0 0 1 2>; /* indicate the crtc mask of osd plane */
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crtcmask_of_video = <0 1 2>; /* indicate the crtc mask of video plane */
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vpu_topology: vpu_topology {
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vpu_blocks {
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osd1_block: block@0 {
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id = /bits/ 8 <OSD1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <0>;
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block_name = "osd1_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &afbc1_block>;
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};
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osd2_block: block@1 {
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id = /bits/ 8 <OSD2_BLOCK>;
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index = /bits/ 8 <1>;
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type = /bits/ 8 <0>;
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block_name = "osd2_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <1 &afbc1_block>;
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};
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osd3_block: block@2 {
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id = /bits/ 8 <OSD3_BLOCK>;
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index = /bits/ 8 <2>;
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type = /bits/ 8 <0>;
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block_name = "osd3_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &afbc2_block>;
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};
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osd4_block: block@3 {
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id = /bits/ 8 <OSD4_BLOCK>;
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index = /bits/ 8 <3>;
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type = /bits/ 8 <0>;
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block_name = "osd4_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &afbc3_block>;
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};
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afbc1_block: block@4 {
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id = /bits/ 8 <AFBC1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <1>;
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block_name = "afbc1_block";
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num_in_links = /bits/ 8 <0x2>;
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in_links = <0 &osd1_block>,
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<0 &osd2_block>;
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num_out_links = /bits/ 8 <0x2>;
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out_links = <0 &osd_blend_block>,
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<0 &scaler2_block>;
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};
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afbc2_block: block@5 {
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id = /bits/ 8 <AFBC2_BLOCK>;
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index = /bits/ 8 <1>;
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type = /bits/ 8 <1>;
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block_name = "afbc2_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &osd3_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &scaler3_block>;
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};
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afbc3_block: block@6 {
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id = /bits/ 8 <AFBC3_BLOCK>;
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index = /bits/ 8 <2>;
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type = /bits/ 8 <1>;
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block_name = "afbc3_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &osd4_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &scaler4_block>;
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};
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scaler1_block: block@7 {
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id = /bits/ 8 <SCALER1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <2>;
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block_name = "scaler1_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &hdr1_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &vpp1_postblend_block>;
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};
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scaler2_block: block@8 {
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id = /bits/ 8 <SCALER2_BLOCK>;
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index = /bits/ 8 <1>;
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type = /bits/ 8 <2>;
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block_name = "scaler2_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <1 &afbc1_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <1 &osd_blend_block>;
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};
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scaler3_block: block@9 {
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id = /bits/ 8 <SCALER3_BLOCK>;
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index = /bits/ 8 <2>;
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type = /bits/ 8 <2>;
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block_name = "scaler3_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &afbc2_block>;
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num_out_links = /bits/ 8 <0x2>;
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out_links = <2 &osd_blend_block>,
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<0 &hdr2_block>;
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};
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scaler4_block: block@10 {
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id = /bits/ 8 <SCALER4_BLOCK>;
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index = /bits/ 8 <3>;
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type = /bits/ 8 <2>;
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block_name = "scaler4_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &afbc3_block>;
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num_out_links = /bits/ 8 <0x2>;
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out_links = <3 &osd_blend_block>,
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<0 &vpp3_postblend_block>;
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};
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osd_blend_block: block@11 {
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id = /bits/ 8 <OSD_BLEND_BLOCK>;
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block_name = "osd_blend_block";
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type = /bits/ 8 <3>;
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num_in_links = /bits/ 8 <0x4>;
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in_links = <0 &afbc1_block>,
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<0 &scaler2_block>,
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<0 &scaler3_block>,
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<0 &scaler4_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &hdr1_block>;
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};
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hdr1_block: block@12 {
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id = /bits/ 8 <HDR1_BLOCK>;
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index = /bits/ 8 <0>;
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block_name = "hdr1_block";
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type = /bits/ 8 <4>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &osd_blend_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &scaler1_block>;
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};
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hdr2_block: block@13 {
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id = /bits/ 8 <HDR2_BLOCK>;
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index = /bits/ 8 <1>;
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block_name = "hdr2_block";
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type = /bits/ 8 <4>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <1 &osd_blend_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &vpp2_postblend_block>;
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};
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vpp1_postblend_block: block@14 {
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id = /bits/ 8 <VPP1_POSTBLEND_BLOCK>;
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index = /bits/ 8 <0>;
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block_name = "vpp1_postblend_block";
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type = /bits/ 8 <6>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &scaler1_block>;
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num_out_links = <0x0>;
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};
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vpp2_postblend_block: block@15 {
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id = /bits/ 8 <VPP2_POSTBLEND_BLOCK>;
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index = /bits/ 8 <1>;
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block_name = "vpp2_postblend_block";
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type = /bits/ 8 <6>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <1 &hdr2_block>;
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num_out_links = <0x0>;
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};
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vpp3_postblend_block: block@16 {
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id = /bits/ 8 <VPP3_POSTBLEND_BLOCK>;
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index = /bits/ 8 <2>;
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block_name = "vpp3_postblend_block";
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type = /bits/ 8 <6>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &scaler4_block>;
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num_out_links = <0x0>;
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};
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video1_block: block@17 {
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id = /bits/ 8 <VIDEO1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <7>;
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block_name = "video1_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x0>;
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};
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video2_block: block@18 {
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id = /bits/ 8 <VIDEO2_BLOCK>;
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index = /bits/ 8 <1>;
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type = /bits/ 8 <7>;
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block_name = "video2_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x0>;
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};
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video3_block: block@19 {
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id = /bits/ 8 <VIDEO3_BLOCK>;
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index = /bits/ 8 <2>;
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type = /bits/ 8 <7>;
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block_name = "video3_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x0>;
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};
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};
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};
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vpu_hw_para: vpu_hw_para@0 {
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osd_ver = /bits/ 8 <OSD_V7>;
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afbc_type = /bits/ 8 <0x2>;
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has_deband = /bits/ 8 <0x1>;
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has_lut = /bits/ 8 <0x1>;
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has_rdma = /bits/ 8 <0x1>;
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osd_fifo_len = /bits/ 8 <64>;
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vpp_fifo_len = /bits/ 32 <0xfff>;
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};
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};
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};
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&amhdmitx {
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmitx_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_hdmitx>;
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};
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};
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};
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};
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@@ -6,6 +6,7 @@
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/dts-v1/;
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#include "mesont7c.dtsi"
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#include "mesont7c_drm.dtsi"
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#include "partition_mbox_ab.dtsi"
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#include <dt-bindings/input/input.h>
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#include "mesont7_an400-panel.dtsi"
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@@ -1630,7 +1631,7 @@
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};
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&fb {
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status = "okay";
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status = "disabled";
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display_size_default = <3840 2160 3840 4320 32>;
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mem_size = <0x00800000 0x4000000 0x100000 0x100000 0x100000>;
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4k2k_fb = <1>;
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@@ -1640,6 +1641,61 @@
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pxp_mode = <0>; /** 0:normal mode 1:pxp mode */
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};
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&drm_vpu {
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status = "okay";
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logo_addr = "0x3f800000";
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connectors_dev: port@1 {
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drm_to_lcd0: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&lcd0_to_drm>;
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};
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drm_to_lcd1: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&lcd1_to_drm>;
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};
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drm_to_lcd2: endpoint@4 {
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reg = <4>;
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remote-endpoint = <&lcd2_to_drm>;
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};
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};
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};
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&lcd {
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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lcd0_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_lcd0>;
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};
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};
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};
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};
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&lcd1 {
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ports {
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port {
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lcd1_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_lcd1>;
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};
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};
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};
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};
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&lcd2 {
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ports {
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port {
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lcd2_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_lcd2>;
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};
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};
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};
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};
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&amvideom {
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display_device_cnt = <2>;
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vpp0_layer_count = <2>;
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