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video: add vd2 film grian support for s6 [1/1]

Browse Source 
PD#SWPL-173004

Problem:
add vd2 film grain support

Solution:
complete it

Verify:
s6

Change-Id: I526d43147472144d774a01123d8a8b174bea17e8
Signed-off-by: yuhua.lin <yuhua.lin@amlogic.com>
This commit is contained in:
yuhua.lin
2024-06-17 14:10:09 +08:00
committed by Luan Yuan
parent 45a4bf1995
commit e5e3e968d0
3 changed files with 23 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/video_sink/video.c
+3 -3
View File
@@ -14838,7 +14838,7 @@ static struct amvideo_device_data_s amvideo_s6 = {
.core_v_enable_width_max[1] = 2048,
.supscl_path = VSR_BEFORE_VE,
.fgrain_support[0] = 1,
.fgrain_support[1] = 0,
.fgrain_support[1] = 1,
.fgrain_support[2] = 0,
.has_hscaler_8tap[0] = 1,
.has_hscaler_8tap[1] = 1,
@@ -14850,10 +14850,10 @@ static struct amvideo_device_data_s amvideo_s6 = {
.has_pre_vscaler_ntap[1] = 1,
.has_pre_vscaler_ntap[2] = 0,
.src_width_max[0] = 4096,
.src_width_max[1] = 2048,
.src_width_max[1] = 4096,
.src_width_max[2] = 2048,
.src_height_max[0] = 2160,
.src_height_max[1] = 1080,
.src_height_max[1] = 2160,
.src_height_max[2] = 1080,
.ofifo_size = 0x1000,
.afbc_conv_lbuf_len[0] = 0x100,
drivers/media/video_sink/video_hw.c
+16 -6
View File
@@ -2123,7 +2123,7 @@ static void vd1_set_dcu(struct video_layer_s *layer,
u32 pat, loop;
static const u32 vpat[MAX_VSKIP_COUNT + 1] = {
0, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
u32 u, v;
u32 y, u, v;
u32 type, bit_mode = 0, canvas_w;
bool is_mvc = false;
u8 burst_len = 1;
@@ -2258,7 +2258,8 @@ static void vd1_set_dcu(struct video_layer_s *layer,
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
if (vf &&
(vf->source_type != VFRAME_SOURCE_TYPE_HDMI &&
!IS_DI_POSTWRTIE(vf->type)))
(!IS_DI_POSTWRTIE(vf->type) &&
!(vf->flag & VFRAME_FLAG_COMPOSER_DONE))))
r |= (1 << 19); /* dos_uncomp */
if (type & VIDTYPE_COMB_MODE)
r |= (1 << 20);
@@ -2279,9 +2280,13 @@ static void vd1_set_dcu(struct video_layer_s *layer,
u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
if (vf->flag & VFRAME_FLAG_COMPOSER_DONE)
y = 0;
else
y = 0x3FF;
cur_dev->rdma_func[vpp_index].rdma_wr
(vd_afbc_reg->afbc_dec_def_color,
0x3FF00000 | /*Y,bit20+*/
y << 20 | /*Y,bit20+*/
0x80 << (u + 10) |
0x80 << v);
/* chroma formatter */
@@ -2739,7 +2744,7 @@ static void vdx_set_dcu(struct video_layer_s *layer,
u32 pat, loop;
static const u32 vpat[MAX_VSKIP_COUNT + 1] = {
0, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
u32 u, v;
u32 y, u, v;
u32 type, bit_mode = 0, canvas_w;
bool is_mvc = false;
u8 burst_len = 1;
@@ -2823,7 +2828,8 @@ static void vdx_set_dcu(struct video_layer_s *layer,
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
if (vf &&
(vf->source_type != VFRAME_SOURCE_TYPE_HDMI &&
!IS_DI_POSTWRTIE(vf->type)))
(!IS_DI_POSTWRTIE(vf->type) &&
!(vf->flag & VFRAME_FLAG_COMPOSER_DONE))))
r |= (1 << 19); /* dos_uncomp */
if (type & VIDTYPE_COMB_MODE)
r |= (1 << 20);
@@ -2844,9 +2850,13 @@ static void vdx_set_dcu(struct video_layer_s *layer,
u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
if (vf->flag & VFRAME_FLAG_COMPOSER_DONE)
y = 0;
else
y = 0x3FF;
cur_dev->rdma_func[vpp_index].rdma_wr
(vd_afbc_reg->afbc_dec_def_color,
0x3FF00000 | /*Y,bit20+*/
y << 20 | /*Y,bit20+*/
0x80 << (u + 10) |
0x80 << v);
drivers/media/video_sink/video_safa.c
+4 -2
View File
@@ -1017,7 +1017,9 @@ static void set_vd1_frm2fld_en(struct vsr_setting_s *vsr)
u8 vpp_index = vsr->vpp_index;
struct vinfo_s *vinfo = get_current_vinfo();
u32 frm2fld_en = 0;
struct hw_vsr_safa_reg_s *vsr_reg;
vsr_reg = &vd_layer[0].vsr_safa_reg;
if (vinfo->field_height != vinfo->height && cur_dev->frm2fld_support)
frm2fld_en = 1;
if (frm2fld_en) {
@@ -1031,7 +1033,7 @@ static void set_vd1_frm2fld_en(struct vsr_setting_s *vsr)
*/
cur_dev->rdma_func[vpp_index].rdma_wr(VPP_P2I_H_V_SIZE,
vsr->vsr_top.hsize_out << 16 | vsr->vsr_top.vsize_out);
cur_dev->rdma_func[vpp_index].rdma_wr_bits(SAFA_PPS_HW_CTRL,
cur_dev->rdma_func[vpp_index].rdma_wr_bits(vsr_reg->safa_pps_hw_ctrl,
1, 26, 1);
}
}
@@ -1042,7 +1044,7 @@ static void sharpness_and_dir_interp_enable(void)
struct hw_vsr_safa_reg_s *vsr_reg;
rdma_wr_bits_op rdma_wr_bits = cur_dev->rdma_func[vpp_index].rdma_wr_bits;
vsr_reg = &vsr_safa_reg;
vsr_reg = &vd_layer[0].vsr_safa_reg;
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
safa_dir_interp_en, 25, 1);
if (super_scaler)