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https://github.com/hardkernel/kernel_common_drivers.git
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vpu: add 888M clk for t6x [1/1]
PD#SWPL-239174 Problem: add 888M clk for t6x vpu Solution: complete it Verify: t6x Change-Id: I0ee2d1248215d860d7929a2f60ac2690cdc53919 Signed-off-by: yuhua.lin <yuhua.lin@amlogic.com>
This commit is contained in:
yuhua.lin
committed by
gerrit autosubmit
gerrit autosubmit
parent
57c536fb68
commit
eeb0b520e4
@@ -1200,19 +1200,21 @@
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<&clkc CLKID_VAPB>,
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_VPU_1>,
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<&clkc CLKID_VPU>;
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<&clkc CLKID_VPU>,
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<&clkc CLKID_GP1_PLL>;
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clock-names = "vapb_clk0",
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"vapb_clk1",
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"vapb_clk",
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"vpu_clk0",
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"vpu_clk1",
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"vpu_clk";
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"vpu_clk",
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"gp_pll";
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overclock_sel = <2>;
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/* 0: force disable 1:force enable 2: adaptable */
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clk_level = <10>;
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clk_level = <9>;
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/* 0: 24.0M 1: 100.0M 2: 166.7M 3: 200.0M 4: 250.0M */
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/* 5: 333.3M 6: 400.0M 7: 500.0M 8: 666.7M 9: 800.0M*/
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/* 10: 840M 11: 808M*/
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/* 10: 840M 11: 808M 12:744M 13:888M*/
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};
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/*if you want to use vdin just modify status to "ok"*/
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@@ -300,8 +300,8 @@ unsigned int rx_switch_vpu_clk(int over_clock_flag)
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int vdin_status;
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unsigned long new_freq;
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if (vpu_conf.data->chip_type == VPU_CHIP_T6X) {
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VPUPR("%s %d over_clock_flag:%d\n", __func__, __LINE__, over_clock_flag);
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if (vpu_conf.data->chip_type == VPU_CHIP_T6X && vpu_conf.vpu_overclock == 2) {
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VPUPR("over_clock_flag:%d\n", over_clock_flag);
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if (vpu_conf.overclock_sel == 0) {
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clk_level = 10;
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} else if (vpu_conf.overclock_sel == 1) {
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@@ -318,20 +318,19 @@ unsigned int rx_switch_vpu_clk(int over_clock_flag)
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}
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}
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} else {
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VPUERR("%s unknown overclock_sel:%d\n", __func__, vpu_conf.overclock_sel);
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VPUERR("unknown overclock_sel:%d\n", vpu_conf.overclock_sel);
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}
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if (clk_level != vpu_conf.clk_level) {
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new_freq = get_vpu_clk_freq(clk_level);
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vpu_clk_info.new_freq = new_freq;
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if (new_freq == 892000000) {
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if (new_freq == 888000000) {
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vd_signal_notifier_call_chain(VIDEO_VPU_CLK_CHANGED,
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&vpu_clk_info);
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/* vdin_status 0:idle 1:vdin 0 worked 2:vdin1 worked */
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vdin_status = get_vdin_status(1);
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if (vdin_status || vpu_debug_print_flag)
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VPUPR("%s, vdin_status:%d\n",
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__func__, vdin_status);
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VPUPR("vdin_status:%d\n", vdin_status);
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set_vpu_clk(clk_level);
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} else if (new_freq == 840000000) {
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set_vpu_clk(clk_level);
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@@ -852,7 +851,12 @@ static void set_vpu_overclk(void)
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if (vpu_conf.data->chip_type == VPU_CHIP_T6X) {
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vpu_max_freq = efuse_amlogic_cali_item_read(EFUSE_CALI_SUBITEM_VPU_MAXFREQ);
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VPUPR("%s vpu support max freq: %d\n", __func__, vpu_max_freq);
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vpu_conf.vpu_overclock = (vpu_max_freq == 180) ? 1 : 0;
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if (vpu_max_freq == 170)
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vpu_conf.vpu_overclock = 1;
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else if (vpu_max_freq == 180)
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vpu_conf.vpu_overclock = 2;
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else
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vpu_conf.vpu_overclock = 0;
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}
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}
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@@ -1643,6 +1647,13 @@ static ssize_t vpu_debug_print_store(const struct class *class,
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return count;
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}
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static ssize_t vpu_overclock_show(const struct class *class,
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const struct class_attribute *attr, char *buf)
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{
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return sprintf(buf, "vpu overclock: %d\n",
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vpu_conf.vpu_overclock);
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}
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static ssize_t vpu_arb_bind_store(const struct class *class,
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const struct class_attribute *attr,
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const char *buf, size_t count)
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@@ -1917,6 +1928,7 @@ static struct class_attribute vpu_debug_class_attrs[] = {
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__ATTR(sideband_level, 0644, vpu_sideband_level_show, vpu_sideband_level_store),
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__ATTR(sideband_block_device, 0644, vpu_sideband_block_device_show,
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vpu_sideband_block_device_store),
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__ATTR(overclock, 0444, vpu_overclock_show, NULL),
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__ATTR(help, 0444, vpu_debug_help, NULL),
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};
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@@ -1976,6 +1988,9 @@ static int get_vpu_config(struct platform_device *pdev)
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val = vpu_conf.data->clk_level_dft;
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}
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if (vpu_conf.data->chip_type == VPU_CHIP_T6X &&
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vpu_conf.vpu_overclock)
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val = 10;
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vpu_conf.clk_level = val;
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}
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VPUPR("load vpu_clk: %uHz(%u)\n",
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@@ -3216,7 +3231,7 @@ static struct vpu_data_s vpu_data_t6x = {
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.power_init_check = vpu_power_init_check_dft,
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.mempd_switch = vpu_vmod_mem_pd_switch_new,
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.mempd_get = vpu_vmod_mem_pd_get_new,
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.clk_apply = vpu_clk_apply_dft,
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.clk_apply = vpu_clk_apply_t6x,
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.clktree_init = vpu_clktree_init_dft,
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};
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@@ -204,6 +204,7 @@ unsigned long get_vpu_clk_freq(unsigned int clk_level);
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unsigned int get_vpu_clk_level_max_vmod(void);
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unsigned int get_vpu_clk_level_from_venc(unsigned int venc_clk);
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int vpu_clk_apply_dft(unsigned int clk_level);
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int vpu_clk_apply_t6x(unsigned int clk_level);
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int vpu_clk_apply_c3(unsigned int clk_level);
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int set_vpu_clk(unsigned int vclk);
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void vpu_clktree_init_dft(struct device *dev);
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@@ -359,6 +359,69 @@ int vpu_clk_apply_dft(unsigned int clk_level)
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return ret;
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}
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int vpu_clk_apply_t6x(unsigned int clk_level)
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{
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unsigned int clk;
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int ret = 0;
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ret = vpu_chip_valid_check();
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if (ret) {
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ret = 1;
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goto error_out;
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}
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if (vpu_conf.data->clk_table[clk_level].mux == FCLK_DIV_MAX) {
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ret = 2;
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goto error_out;
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}
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if (IS_ERR_OR_NULL(vpu_conf.vpu_clk)) {
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ret = 3;
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goto error_out;
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}
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if (vpu_conf.data->chip_type == VPU_CHIP_T6X) {
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if (IS_ERR_OR_NULL(vpu_conf.gp_pll)) {
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ret = 4;
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goto error_out;
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}
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/* step 1: set vpu clk 800M */
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if (clk_level == 10 || clk_level == 13) {
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clk = vpu_conf.data->clk_table[vpu_conf.data->clk_level_dft].freq;
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ret = clk_set_rate(vpu_conf.vpu_clk, clk);
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if (ret) {
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ret = 5;
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goto error_out;
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}
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}
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/* step 2: set gpl pll clk */
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if (clk_level == 10)
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ret = clk_set_rate(vpu_conf.gp_pll, 1680000000);
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else if (clk_level == 13)
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ret = clk_set_rate(vpu_conf.gp_pll, 1776000000);
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if (ret) {
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ret = 6;
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goto error_out;
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}
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}
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clk = vpu_conf.data->clk_table[clk_level].freq;
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ret = clk_set_rate(vpu_conf.vpu_clk, clk);
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if (ret) {
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ret = 7;
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goto error_out;
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}
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clk = clk_get_rate(vpu_conf.vpu_clk);
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VPUPR("set vpu clk: %uHz(%d), readback: %uHz(0x%x)\n",
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vpu_conf.data->clk_table[clk_level].freq, clk_level,
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clk, (vpu_clk_read(vpu_conf.data->vpu_clk_reg)));
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return 0;
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error_out:
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VPUERR("change vpu clk fail, ret = %d\n", ret);
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return ret;
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}
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int vpu_clk_apply_c3(unsigned int clk_level)
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{
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unsigned int clk;
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@@ -45,8 +45,8 @@
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#define CLK_LEVEL_DFT_T6W 10
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#define CLK_LEVEL_MAX_T6W 12
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#define CLK_LEVEL_DFT_T6X 10
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#define CLK_LEVEL_MAX_T6X 14
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#define CLK_LEVEL_DFT_T6X 9
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#define CLK_LEVEL_MAX_T6X 15
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#ifndef CONFIG_AMLOGIC_C3_REMOVE
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/* vpu clk setting */
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@@ -124,7 +124,7 @@ static struct vpu_clk_s vpu_t6w_clk_table[] = {
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{840000000, GPLL_CLK1, 1}, /* 10 */ /* for t6w gp1 div gp1 1680 to 840M*/
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{808000000, GPLL_CLK2, 0}, /* 11 */ /* for t6w gp2 808M*/
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{744000000, GPLL_CLK, 0}, /* 12 */
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{892000000, GPLL_CLK2, 0}, /* 13 */ /* for t6x gp2 892M*/
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{888000000, GPLL_CLK1, 1}, /* 13 */ /* for t6x gp1 888M*/
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};
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#endif
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#endif
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