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eth: s7 bringup [1/1]

Browse Source 
PD#SWPL-152416

Problem:
s7 bringup

Solution:
s7 bringup

Verify:
S905Y5-BH201_REF#023

Change-Id: Ib12ad0a5fbcb36d3e4c747f742a19a5267e96eaa
Signed-off-by: Zhuo Wang <zhuo.wang@amlogic.com>
This commit is contained in:
Zhuo Wang
2024-01-09 16:00:16 +08:00
committed by Luan Yuan
parent 57248cecc8
commit f3cf68f448
5 changed files with 34 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-s7.dtsi
+21 -20
View File
@@ -1125,18 +1125,20 @@
support-sysrq = <0>; /* 0 not support*/
};
eth_phy: mdio-multiplexer@28000 {
eth_phy: mdio-multiplexer@360000 {
compatible = "amlogic,g12a-mdio-mux";
reg = <0x0 0x28000 0x0 0xa4>;
status = "disabled";
//clocks = <&clkc CLKID_ETHPHY>,
// <&xtal>,
// <&clkc CLKID_MPLL_50M>;
//clock-names = "pclk", "clkin0", "clkin1";
reg = <0x0 0x360000 0x0 0xa4>;
clocks = <&clkc CLKID_SYS_ETHPHY>,
<&xtal>,
<&clkc CLKID_FCLK_CLK50M>;
clock-names = "pclk", "clkin0", "clkin1";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
enet_type = <5>;
phy_pll_mode = <2>;
phy_mode = <3>;
tx_amp_src = <0xFE010330>;
ext_mdio: mdio@0 {
@@ -1499,23 +1501,22 @@
nand_clk_ctrl = <0xfe08c000>;
};
ethmac: ethernet@fdc00000 {
ethmac: ethernet@fe368000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",
"snps,dwmac";
reg = <0x0 0xfdc00000 0x0 0x10000>,
<0x0 0xfe024000 0x0 0x8>;
"snps,dwmac-4.00";
reg = <0x0 0xfe368000 0x0 0x12ec>,
<0x0 0xfe364000 0x0 0x8>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
//power-domains = <&pwrdm PDID_S4_ETH>;
//clocks = <&clkc CLKID_ETH>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_MPLL2>;
//clock-names = "stmmaceth", "clkin0", "clkin1";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
clocks = <&clkc CLKID_SYS_ETHPHY>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_CLK50M>;
clock-names = "stmmaceth", "clkin0", "clkin1";
// mboxes = <&mbox_fifo S1A_REE2AO_ETH>;
snps,force_thresh_dma_mode;
status = "disabled";
analog_version = <1>;
mc_val = <0x180c>;
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
arch/arm64/boot/dts/amlogic/s7_s905y5_bh201.dts
+1 -2
View File
@@ -1531,10 +1531,9 @@
};
&ethmac {
status = "disabled";
status = "okay";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
keep-alive = <1>;
};
&ir {
arch/arm64/boot/dts/amlogic/s7_s905y5_bh202.dts
+1 -2
View File
@@ -1529,10 +1529,9 @@
};
&ethmac {
status = "disabled";
status = "okay";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
keep-alive = <1>;
};
&ir {
arch/arm64/boot/dts/amlogic/s7_s905y5_bh209.dts
+1 -2
View File
@@ -1531,10 +1531,9 @@
};
&ethmac {
status = "disabled";
status = "okay";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
keep-alive = <1>;
};
&ir {
drivers/net/mdio/mdio-mux-meson-g12a.c
+10
View File
@@ -182,6 +182,16 @@ static int g12a_ephy_pll_init(struct clk_hw *hw)
writel(0x508200a0, pll->base + ETH_PLL_CTL0);
writel(0x00000110, pll->base + ETH_PLL_CTL2);
}
/*s7*/
if (phy_pll_mode == 2) {
writel(0x00510630, pll->base + ETH_PLL_CTL0);
writel(0x222210a0, pll->base + ETH_PLL_CTL1);
writel(0x00518630, pll->base + ETH_PLL_CTL0);
usleep_range(100, 200);
writel(0x222200a0, pll->base + ETH_PLL_CTL1);
usleep_range(100, 200);
writel(0x00118630, pll->base + ETH_PLL_CTL0);
}
#else
writel(0x29c0040a, pll->base + ETH_PLL_CTL0);