PD#SWPL-180321
Problem:
there are no usb pll and usb clock
Solution:
add usb pll and usb clock
Verify:
t6d br301
Change-Id: I24f381493a3f8d7d3510252fdc35ab2eb9b09b7e
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-180321
Problem:
it does not support amfc
Solution:
add amfc support
Verify:
t6d br301
Change-Id: Idb0d1d8aa3571402a636bd75018735fcb82bc489
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-180321
Problem:
it does not support gp0/hifi
Solution:
add gp0/hifi support
Verify:
t6d br301
Change-Id: If3bc4b2a0a53eea7447cf4432830ff6f1372ee83
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-180321
Problem:
there is no eth phy clock
Solution:
correct eth phy clock name
Verify:
t6d br301
Change-Id: Ie8ff90cf998c4a8064f01e4e52d63b7e284b4dd3
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-179629
Problem:
1 Optimize driver file formats using automated tools.
2 vpu_clk adds a flag feature to prevent glitch when operating the
clock.
3 The naming of hifi_pll is inconsistent with the clkid style.
4 The latest documentation provided by vlsi has changed the sys_clk
definition for USB and PCIe.
Solution:
1 Optimized
2 vpu_clk added flag CLK_OPS_PARENT_ENABLE.
3 The clkid of hifi_pll is named CLKID_HIFI_PLL.
4 USB and PCIe sys_clk have been updated.
Verify:
s6_bl201
Change-Id: I4560f7bc6d42583d4e62d184c182bfe199cb6955
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-174549
Problem:
secure permission needs to be set for the pwm_clk register
related to voltage regulation. Relevant clk configurations
need to be stored in bl31. kernel configurations need to
be deleted.
Solution:
fix it
Verify:
s7
Change-Id: If3477940b33f4a612743cb1c5c58ce45e59a8505
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-172965
Problem:
1 The mclk0 power supply uses the power supply inside the mclk_pll, so the
mclk0 output must ensure that mclk_pll is also enabled.
mclk_pll_clk can output clocks mclk_pll_src and fclk50m. The existence of
these two clock sources is meaningless.
2 If mclk0 uses mclk_pll as the clock source, div2 must be selected for
the clock of the later stage; otherwise, the output clock waveform of
mclk0 is abnormal.
Solution:
1 Delete the mclk_pll_src and fclk50m clock sources and set mclk_pll_clk
as the clock source of mclk0.
2 mclk0 selects div2 by default.
Verify:
s6_bl201
Change-Id: I9a8e3e1616b4c9b3b9c86990f86dc337f9f9c877
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-172965
Problem:
1 All I2C Masters (i2c_m_a-f) in a chip share an APB bus, which is
provided by sys_i2c_m_a. PWM is designed with a similar architecture, and
the APB bus of PWM is clock provided by sys_pwm_a.
2 The CLKID definition of smart card is inconsistent.
Solution:
1 The parent of sys_i2c_m_b-f is set to sys_i2c_m_a.
2 The parent of sys_pwm_b-i is set to sys_pwm_a.
3 CLKID_SC_DIV was renamed CLKID_SC.
Verify:
s6_bl201
Change-Id: I94482625f3a9fe387113edce21ed16e9dc63a074
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-172965
Problem:
1 mclk_pll and dspa_clk output are incorrect
2 mmc failed to insmod
3 Lost sys_i2c_s_a
Solution:
1 Update the table for mclk_pll
2 Update the parent table of the dspa
3 Ignore initializing gp0_pll
4 Added sys_i2c_s_a
Verify:
s6_bl201
Change-Id: I23586623d908ef871e178acf0da8883aabc12fc9
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-158289
Problem:
1 The register corresponding to oscin was updated;
2 Put some of the key clocks into bl31 for processing.
Solution:
fixed
Verify:
pxp
Change-Id: Ie5ea8b6c507ce136ba397e8e54362b72f05cf45c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-171660
Problem:
S7D fclk_div3 design intent should have been div3 output 666M, in fact
revA designed to div2 output 1G, the issue has been fixed in revB.
Solution:
Fixed
Verify:
s7d_bm209
Change-Id: I6579129141aae7af88bca07758ac343abc5f94c8
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-169674
Problem:
1 The clock driver of the g12a/g12b/sm1 is shared.
2 The YOCTO dual-screen display request of SM1 and G12B assigns gp0_pll
to MIPI DSI.As a result, the GPU cannot use gp0_pll, causing the GPU to
run up to 800M instead of the expected 846M.
Solution:
1 By default, gp0_pll is configured to output 846M under the device tree
node of the GPU in the main dtsi.
2 Check whether gp0_pll is configured by overwriting GPU configuration in
the corresponding dts.
Verify:
g12a_u212
Change-Id: Icd2c60b3c7a6e9d64a6d7ce1dce6928504681676
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-167249
Problem:
The parent of pwm_j_div is incorrect
Solution:
Fixed
Verify:
s4_aq222
Change-Id: I58f245a2d09bf3b15476ea72a675f50ceb40cd7f
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-165771
Problem:
hifi_pll has been initially configured in the bootloader and is being
used by audio. If hifi_pll is reconfigured in the kernel, the sound
will be broken.
Solution:
Add flag CLK_MESON_PLL_IGNORE_INIT for hifi_pll
Verify:
sm1_ac215
Change-Id: I2f79fda0c07312ed2bf1bf6203ac16e82f361e14
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-165773
Problem:
hifi_pll has been initially configured in the bootloader and is being
used by audio. If hifi_pll is reconfigured in the kernel, the sound
will be broken.
Solution:
Add flag CLK_MESON_PLL_IGNORE_INIT for hifi_pll
Verify:
s4_ap222/s4d_ap2322
Change-Id: Id46b72e534958d97431eea44f0795cca22ab09d2
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-165772
Problem:
hifi_pll has been initially configured in the bootloader and is being
used by audio. If hifi_pll is reconfigured in the kernel, the sound
will be broken.
Solution:
Add flag CLK_MESON_PLL_IGNORE_INIT for hifi_pll
Verify:
sc2_ah212
Change-Id: I9989d6c16e590207f6b03658705b088f8a13c8c5
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-166049
Problem:
1.v3 ops enable and set_rate is unnecessary to rewrite all pll
reg, only focus on related bit, pll second enable rewrite od bit,
result to it's real rate changed
2.some clk config incorrect
Solution:
1.use v1 ops to compatible, test pll set_rate, enable/disable ok
2.fix unreasonable config
Verify:
s7
Change-Id: Ic2bc808152250d8596e232d3e5318eff7751d4e4
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-165736
Problem:
hifi_pll has been initially configured in the bootloader and is being
used by audio. If hifi_pll is reconfigured in the kernel, the sound
will be broken.
Solution:
Add flag CLK_MESON_PLL_IGNORE_INIT for hifi_pll
Verify:
s7d_bm201
Change-Id: I430a03dbb115d4d34b0514fb5dae5f22a105132e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-166397
Problem:
there is wrong parameter in PTR_ERR
Solution:
use pll_map instead
Verify:
t5m
Change-Id: I3af1b104ae42431c199d2789ed2f4ca64786d6d6
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-165213
Problem:
The fixpll frequency obtained by sc2 and t7c is incorrect.
Solution:
Fixed
Verify:
sc2_ah212
Change-Id: Ibb1b7435a2dbfa8cb007b34b574fef94dda685cc
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-163050
Problem:
1 The parent of cecb and hcodec is incorrect
2 The vclk2_div register is incorrectly defined
3 no glitch mux does not work properly under certain circumstances
Solution:
1 Fixed
2 Fixed
3 Add CLK_OPS_PARENT_ENABLE to mux whose model is no glitch mux to
ensure that mux0 is enabled during mux switchover
Verify:
s7d_bm209
Change-Id: Ib78e899f7f1a93e1b9db6860c093dd28f1246491
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-158288
Problem:
1 Adding the logic associated with the en0p5 member makes the driver's
processing more complicated and messy.
2 Added clocks with security permissions.
Solution:
1 Only add CLK_MESON_PLL_FIXED_EN0P5 flag to implement the functions
of en0p5, so that the driver change cost is minimal.
2 Determine whether to add the CLK_MESON_PLL_FIXED_EN0P5 flag based
on whether en0p5 is enabled in init_regs.
3 Added scmi clocks
Verify:
pxp
Change-Id: I2f9e258569f4bed44cb5fd9b57368dbfa3c425cb
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-163564
Problem:
hdmitx and audio need hifipll set to 491.52M in uboot.
Solution:
set s5 hifi to 491.52M in bl2, and ignore hifipll init in kernel,
donot close it when booting
Verify:
s5
Change-Id: I487c9160e25bc0869ed6f72b557ca8d0c3456273
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-153316
Problem:
hifi need 491.52M by hdmitx and audio
Solution:
set hifi to 491.52M in U-boot,
do not touch the hifi parameter in Kernel
Verify:
t7 an400
Change-Id: I0841fa8cda45bb763144b78a1b0ed5d272a5c12b
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-144045
Problem:
sys2 pll does not support 828MHz
Solution:
add sys2 pll 828M support
Verify:
t3x
Change-Id: I380c829da4ff32fc063e6f98e787456532e49fc6
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-157952
Problem:
second enable pll will call set_rate, it reset od use init_regs
od bit, result pll rate changed
Solution:
store pll od when set_rate and rewrite it to regwith
other parm through enable
Verify:
s7_bh201
Change-Id: I04c236f3fd716fcf9b3ef1442eba8a5565dcdb02
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-160104
Problem:
add clk_ignore_unused flag to not disable pwm clk
when kernel boot
Solution:
add clk_ignore_unused flag
Verify:
s7
Change-Id: I174d24a22e9e8559f9622f6aaa4ab3cad8b0e118
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-157599
Problem:
In special scenarios (such as low-temperatures), lock may fail after pll is
configured. Therefore, the retry mechanism is added to ensure that pll lock
can be successfully configured.
Solution:
Add the retry mechanism and allow a maximum of 10 retry times after the pll
lock fails.
Verify:
a4_ba400
Change-Id: I6218f959a37252b50be126d93a9ff5b22b074f92
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-155614
Problem:
s4 hifi_pll add flag to protect its sub-clk
change rate when set hifi_pll rate
Solution:
fix it
Verify:
s4_aq222
Change-Id: Ib2c8e584102c55bc8070f8054799e90047a7d9fb
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-154300
Problem:
s7 mali no switch mux_a and mux_b causes
mali gpu probability reset
Solution:
add flag switch mux_a and mux_b
Verify:
s7
Change-Id: I06f8d3d9b74022b0934fd5aa52dba4aacd92190c
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-152400
Problem:
modify the clk measure according to the
latest clktree document
Solution:
fix it
Verify:
s7
Change-Id: I53d14d0d7202807177314ad73bdbc7ec7bb0eb6a
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
Jian Hu