PD#SWPL-201096
Problem:
there's probability 10or18to20 fifo over/under flow
issue during display, and will cause flash screen issue
1.10or18to20 fifo reset itself will cause fifo
spill over again
2.clk_todig(the fifo put clk) is disable when disable phy
3.hpll may be unlock after switch mode, especially when
hpll fractional part is large.
Solution:
optimise 10to20 fifo
1.disable fifo intr before do fifo reset, and add delay
after fifo reset and before enable fifo intr again
2.keep clk_todig always enabled
3.increase pll lock tolerance of hpll fractional part
Verify:
s5
Test:
DRM-TX-78 DRM-TX-79
Change-Id: Ib678d77e205e3dd8e54bd44955c22e4527689e2f
Signed-off-by: hang cheng <hang.cheng@amlogic.com>
PD#SWPL-200524
Problem:
used brr_duration to calc reshape skip if QMS enable
Solution:
used brr_duration to calc reshape skip if QMS enable
Verify:
s5
Test:
s5 QMS mode play video
Change-Id: If443599dd27e5ed78247b98bfc07038137254b24
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
Signed-off-by: zongdong.jiao <zongdong.jiao@amlogic.com>
PD#SWPL-197630
Problem:
When there are multiple owners, the slots and scatter
released by one owner will not be fully released.
Solution:
release no user scatters, no matter how many there are.
Verify:
sc2
Change-Id: I8d0a9cef75e53cdfd78fc39beb064265526b5b10
Signed-off-by: Hao Shi <hao.shi@amlogic.com>
PD#SWPL-199252
Problem:
memory leaks because repeat vf could not signal fence
Solution:
drop err vf when next vsync comes
Verify:
T5M
Change-Id: I90688285da91b7192d4d3c3d4c7426082efd38bb
Signed-off-by: zhenteng.tian <zhenteng.tian@amlogic.com>
PD#SWPL-197836
Problem:
AndroidU framework get hdmi connect status by the node:
cat /sys/class/extcon/extcon0/cable.0/state;
now only the hpd plugout will send extcon node 0;
When suspend and hpd is high, the node is 1, so androidU
framework think hdmi is connected
Solution:
hdmitx_audio_event send 0 by extcon when suspend
Verify:
s7d
Test:
DRM-TX-143
Change-Id: I59833796c74b2640b44beb77a7472bcbfc1dd9ca
Signed-off-by: Wenjie Qiao <wenjie.qiao@amlogic.com>
PD#SWPL-199604
Problem:
No prime_sl support
Solution:
YAdd prime_sl support
Verify:
Verified on sc2
Change-Id: I757a0df4f5956f05f9023f5fc5f993140e92bbd5
Signed-off-by: can.zhang <can.zhang@amlogic.com>
PD#SWPL-196463
Problem:
S7 adds the dymanical clock gate of vpfdet. When enable this gate,
it will need extra 1 frame time for accurate timing detection.
Solution:
Enlarge time for vpfdet working
Verify:
s7/qurra
Test:
DRM-TX-75
Change-Id: I1580ea20cd8a1fcfc8047c1dd9826b472f98012f
Signed-off-by: zongdong.jiao <zongdong.jiao@amlogic.com>
PD#SWPL-194999
Problem:
check the deep color phase may make time out
Solution:
enable phy to dig before poll reg
keep the tmds clk and pixel clk
Verify:
s6/s7d
Test:
DRM-TX-135
Change-Id: I09dc3e933d07e3d5aa490fbf35b260fdad10b3a7
Signed-off-by: Wenjie Qiao <wenjie.qiao@amlogic.com>
PD#SWPL-188132
Problem:
check the deep color phase may make mistake
Solution:
not use the intr2_stat1, because from stable to non-stable or vice-versa
the bit will not be 1; and should use the reg SYS_STAT bit0 p_stable
and enable phy to dig before poll reg
Verify:
s5/s7d
Test:
DRM-TX-135
Change-Id: I69882915c7d7ec7c3734e670a813d5bf817e1c79
Signed-off-by: Wenjie Qiao <wenjie.qiao@amlogic.com>
PD#SWPL-207086
Problem:
When OTT is connected to a TV that supports hdr10plus and it is
turned on for the first time, it shows that it does not support
hdr10plus
Solution:
remove the is_hdr10plus_enable judgment logic,
add the enable_hdr10plus node in the amhdmitx device tree to
perform hdr10plus logic judgment
Verify:
t7c
Test:
DRM-TX-78
Change-Id: I3954e5ffabd037f7fa2db6f52cba4467a171b87a
Signed-off-by: ruofei.zhao <ruofei.zhao@amlogic.com>
PD#OTT-75696
PD#SWPL-207086
Problem:
When OTT is connected to a TV that supports hdr10plus and it is
turned on for the first time, it shows that it does not support
hdr10plus
Solution:
remove the is_hdr10plus_enable judgment logic,
add the enable_hdr10plus node in the amhdmitx device tree to
perform hdr10plus logic judgment
Verify:
S905X5
Test:
DRM-TX-78
Change-Id: Ie4bf4d0d9d61287a339b35f1b8c5ad973e2b855f
Signed-off-by: ruofei.zhao <ruofei.zhao@amlogic.com>
PD#OTT-75696
PD#SWPL-207086
Problem:
When OTT is connected to a TV that supports hdr10plus and it is
turned on for the first time, it shows that it does not support
hdr10plus
Solution:
remove the is_hdr10plus_enable judgment logic,
HDR10plus strategy selection by HDR module
Verify:
S905X5
Change-Id: I895a50655b103b3b55aee561e22f4ceb9b9c4727
Signed-off-by: can.zhang <can.zhang@amlogic.com>
PD#SWPL-166694
Problem:
support aisr based on DI backend for t3.
Solution:
support aisr based on DI backend for t3.
Verify:
t3
Change-Id: Idb5e0ab48b0976399e03c183f8ae54d0c136e864
Signed-off-by: qiyao.zhou <qiyao.zhou@amlogic.com>
PD#SWPL-198828
Problem:
switch eye protect mode, color not change when dv enable
Solution:
add eye protect support when dv enable, except sink-led
Verify:
s905x4
Change-Id: I8e9a2d805cf6f1cd21410a86046d6779e5dec51f
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#SWPL-193867
Problem:
update tee protect mem api.
Solution:
use tee_protect_mm().
Verify:
local.
Change-Id: Id7e537d0f6f1fc3ec044e791c3416d730f67ca4c
Signed-off-by: Jianxiong Pan <jianxiong.pan@amlogic.com>
PD#SWPL-179193
Problem:
pcie white list not work.
Solution:
init the specified memory area.
Verify:
local.
Change-Id: Id01c40c7f3403246302fd968611424d9b07d8dd1
Signed-off-by: Jianxiong Pan <jianxiong.pan@amlogic.com>
PD#SWPL-193316
Problem:
secure permission needs to be set for the pwm_clk register
related to voltage regulation. Relevant clk configurations
need to be stored in bl31. kernel configurations need to
be deleted.
Solution:
fix pwm clk related to voltage regulation to secure
cherry-pick from 493051
Verify:
s6_bl201
Change-Id: Ic50a19f2e78f5fffd63ee2c4e481fc4b11e43dc9
Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
PD#SWPL-197385
Problem:
pwm change to tee, not to be used
Solution:
use tee pwm
Verify:
s6
Change-Id: I50e05ea96ed5deff09bc62c9701ed709a92ce384
Signed-off-by: jiabin.chen <jiabin.chen@amlogic.com>
(cherry picked from commit a6b90b2ef3)
PD#SWPL-196869
Problem:
when pwm's clk be locked by tee, all pwm should follow tee.
so, should support wifi 32K on pwm tee module.
in case of clk of wifi's pwm channel being locked.
Solution:
add double channel to match wifi 32K legacy used.
Verify:
s6
Change-Id: I09a0ccbdf191ed31f86a6e3fc006672368eedd15
Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
(cherry picked from commit 13fca4e045)
PD#SWPL-193598
Problem:
When the address of shmem in DTB does not match that of BL31, it
supports updating the address of shmem in DTB.
Solution:
Supported
Verify:
S905Y5/S905X5M/S905X5/T950D5
Change-Id: I67836ac85d81a983061975a000e4276cd9a4720b
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-195183
Problem:
1. Kernel clk tree do not know the state if dsp switch its
clk when kernel is in suspend mode. which would cause clk
state error.
2. Permission of accessing pwrctrl register should be enabled in bl2
instead of configure it dynamicly.
Solution:
1. Move clk switch flow from dsp side to kernel.
2. Open permission of accessing pwrctrl register in bl2.
Verify:
sc2
Change-Id: Icfaad81586781af1db874d07d64edee0875c8c27
Signed-off-by: bangzheng.liu <bangzheng.liu@amlogic.com>
PD#SWPL-191710
Problem:
secure permission needs to be set for the pwm_clk register
related to voltage regulation. Relevant clk configurations
need to be stored in bl31. kernel configurations need to
be deleted.
Solution:
fix pwm clk related to voltage regulation to secure
Verify:
s6_bl201
Change-Id: I5d7eb80055a120cfa2342c48dbfc1b7c8d87d1c8
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-198622
Problem:
s6 ddr refresh rate uses dmc sensor temperature control causes system
is stuck and restarts
Solution:
ddr kernel refresh cuts from dmc to soc temperature control
Verify:
s6
Change-Id: If489190a82e88feb1cd981694dd1e6984c265207
Signed-off-by: Liming Xue <liming.xue@amlogic.com>
PD#SWPL-190856
Problem:
safa_pps_hw_ctrl frm2fld_en bit set when hdmi hot plug
Solution:
update safa_pps_hw_ctrl bit when hdmi hot plug
Verify:
s7d
Change-Id: I7277748566d443424abd3a5c9dff169460b80bae
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
PD#SWPL-195404
Problem:
S7 1G lowmem platform need to reduce codec_mm size.
Solution:
The maximum scenario is HEVC 1080i local playback, need 92M.
Verify:
S7
Change-Id: I2cc57e46694e6a11c4aa42ec9d7ff96af0cf44b2
Signed-off-by: yu.xie <yu.xie@amlogic.com>
PD#SWPL-196548
Problem:
In the Kernel, reading and writing SCMI shmem is non-cache, but in bl31
it is cache. Therefore, it will cause an abnormal SCMI communication
between BL31 and the Kernel due to the cache synchronization issue.
Solution:
SCMI shmem of bl31 is changed to non-cache.
Verify:
S905Y5/S905X5M/S905X5/T950D5
Change-Id: I3cdc18ba22916c84620a154dc616b0f13f4f91f7
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-196371
Problem:
Under AV signal source, there is image but no sound
Solution:
when tdm input source switch acodec, need clear the config
Verify:
t6d
Change-Id: I86d2b9983c50cffad7ed76142dc6b646f6dcd82c
Signed-off-by: jiebing chen <jiebing.chen@amlogic.com>
PD#SWPL-196919
Problem:
the system reboots while playing video
Solution:
move sleepable operations to the work queue
Verify:
s7d
Change-Id: I6671cc5ead066bf03c0c4f803eb7ea3dab2a8ebe
Signed-off-by: Jian Cao <jian.cao@amlogic.com>
PD#SWPL-195250
Problem:
dsp not free memory of reserved in dts when this board not have dsp
Solution:
free reserved memory when soc not have dsp
Verify:
s5
Change-Id: Iea84982c729b5acbbe5d7ad9ac203f3d27f9f839
Signed-off-by: Liming Xue <liming.xue@amlogic.com>
PD#SWPL-197333
Problem:
s6 ddr dmc init register,the write operation will cause the system to
freeze and restart
Solution:
disable ddr control
Verify:
s6
Change-Id: I600aa962619ce8a3de0152c6e36752a33789daab
Signed-off-by: Liming Xue <liming.xue@amlogic.com>
PD#SWPL-195917
Problem:
slabtrace is no longer needed to track slab leaks.
Solution:
disable slabtrace.
use slub debug to trace slab leaks.
Verify:
local.
Change-Id: I6c24505486765f8e0a492b5d027dd5451ee17c75
Signed-off-by: Jianxiong Pan <jianxiong.pan@amlogic.com>
hang cheng