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hang cheng
dcc3320ceb
PD#SWPL-201096 Problem: there's probability 10or18to20 fifo over/under flow issue during display, and will cause flash screen issue 1.10or18to20 fifo reset itself will cause fifo spill over again 2.clk_todig(the fifo put clk) is disable when disable phy 3.hpll may be unlock after switch mode, especially when hpll fractional part is large. Solution: optimise 10to20 fifo 1.disable fifo intr before do fifo reset, and add delay after fifo reset and before enable fifo intr again 2.keep clk_todig always enabled 3.increase pll lock tolerance of hpll fractional part Verify: s5 Test: DRM-TX-78 DRM-TX-79 Change-Id: Ib678d77e205e3dd8e54bd44955c22e4527689e2f Signed-off-by: hang cheng <hang.cheng@amlogic.com>