Jian Hu 628eebb0c6 clk: optimize sys pll setting time [1/1]
PD#SWPL-136018

Problem:
optimize sys pll setting

Solution:
1.remove the unused frequency
2.remove cpu_dyn_clk 1G settings, add
it in probe avoid cpu is 24M during dvfs
3.remove deadcode in clk-pll.c

Verify:
t3x

Change-Id: I64ee9483b1821410029d315f06b83f9748009db3
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
2023-08-13 21:58:36 -07:00
2023-08-11 01:15:30 -07:00
2023-08-08 08:09:27 -07:00
S
Description
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118 MiB
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