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628eebb0c6638cb9f4e1ae8fd36ca5ef472a0709
PD#SWPL-136018 Problem: optimize sys pll setting Solution: 1.remove the unused frequency 2.remove cpu_dyn_clk 1G settings, add it in probe avoid cpu is 24M during dvfs 3.remove deadcode in clk-pll.c Verify: t3x Change-Id: I64ee9483b1821410029d315f06b83f9748009db3 Signed-off-by: Jian Hu <jian.hu@amlogic.com>
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