PD#SWPL-163105
Problem:
new earc Rx design
Solution:
changelist from https://scgit.amlogic.com/#/c/417153
1. new default setting for arc in
2. remove pll refresh when startup
3. when cmdc init, need refresh pll after pll default setting
4. force channel sync for channel mapping
5. add dmac bit29 check for common arc check
6. add iec raw channel status check
7. use chip info(arc_ch_sync/arc_in_new)
Verify:
use s7d
Change-Id: Id681334bfde57bfe71a870a16859e24712e262e3
Signed-off-by: qing.zhang <qing.zhang@amlogic.com>
qing.zhang
861319cbd6