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arm64: dts: rockchip: rk3588: Add edp1 node

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Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I0b2f854d5a283a18c96bf77242cf119cb42800cf
This commit is contained in:
Wyon Bi
2021-09-22 15:30:40 +08:00
committed by Tao Huang
parent 1ba6338e22
commit 011c042f60
1 changed files with 19 additions and 1 deletions
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20
arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -7,6 +7,8 @@
/ {
aliases {
edp0 = &edp0;
edp1 = &edp1;
ethernet0 = &gmac0;
hdptx0 = &hdptxphy0;
hdptx1 = &hdptxphy1;
@@ -79,7 +81,7 @@
hdptxphy1_grf: syscon@fd5e4000 {
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
reg = <0x0 0xfd5e4000 0x0 0x80>;
reg = <0x0 0xfd5e4000 0x0 0x100>;
};
spdif_tx5: spdif-tx@fddb8000 {
@@ -190,6 +192,22 @@
status = "disabled";
};
edp1: edp@fded0000 {
compatible = "rockchip,rk3588-edp";
reg = <0x0 0xfded0000 0x0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>,
<&cru CLK_EDP1_200M>;
clock-names = "dp", "pclk", "spdif";
resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>;
reset-names = "dp", "apb";
phys = <&hdptxphy1>;
phy-names = "dp";
power-domains = <&power RK3588_PD_VO1>;
rockchip,grf = <&vo1_grf>;
status = "disabled";
};
pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;