shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 11:26:02 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rk3588s: Add edp0 node

Browse Source 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ie3bf343524a958bb78842941bcb47f9e3cbe2262
This commit is contained in:
Wyon Bi
2021-09-22 15:02:19 +08:00
committed by Tao Huang
parent 721f665968
commit 1ba6338e22
1 changed files with 22 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -356,6 +356,11 @@
reg = <0x0 0xfd5a6000 0x0 0x2000>;
};
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
};
usb_grf: syscon@fd5ac000 {
compatible = "rockchip,rk3588-usb-grf", "syscon";
reg = <0x0 0xfd5ac000 0x0 0x4000>;
@@ -452,7 +457,7 @@
hdptxphy0_grf: syscon@fd5e0000 {
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
reg = <0x0 0xfd5e0000 0x0 0x80>;
reg = <0x0 0xfd5e0000 0x0 0x100>;
};
ioc: syscon@fd5f0000 {
@@ -1106,6 +1111,22 @@
status = "disabled";
};
edp0: edp@fdec0000 {
compatible = "rockchip,rk3588-edp";
reg = <0x0 0xfdec0000 0x0 0x1000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
<&cru CLK_EDP0_200M>;
clock-names = "dp", "pclk", "spdif";
resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
reset-names = "dp", "apb";
phys = <&hdptxphy0>;
phy-names = "dp";
power-domains = <&power RK3588_PD_VO1>;
rockchip,grf = <&vo1_grf>;
status = "disabled";
};
pcie2x1l1: pcie@fe180000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;