pwm: rockchip: Make pwm pinctrl setting after pwm enabled

If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM into an intermediate state, destroy the default
hardware state, the PWM is not ready for work yet. So it is better
for doing PWM pinctrl setting after PWM enabled.

Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu
2018-02-25 16:58:56 +08:00
committed by Tao Huang
parent ddce12799c
commit 016e8545af
10 changed files with 55 additions and 38 deletions

View File

@@ -557,7 +557,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
@@ -568,7 +568,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
@@ -579,7 +579,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
@@ -590,7 +590,7 @@
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};

View File

@@ -833,22 +833,22 @@
};
&pwm0 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_out>;
};

View File

@@ -571,22 +571,22 @@
};
&pwm0 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_out>;
};

View File

@@ -575,7 +575,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
@@ -586,7 +586,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
@@ -597,7 +597,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
@@ -609,7 +609,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};

View File

@@ -667,7 +667,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@@ -678,7 +678,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@@ -689,7 +689,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@@ -700,7 +700,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";

View File

@@ -379,7 +379,7 @@
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -391,7 +391,7 @@
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -403,7 +403,7 @@
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -415,7 +415,7 @@
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
#pwm-cells = <3>;
status = "disabled";

View File

@@ -512,7 +512,7 @@
reg = <0x0 0xff1b0000 0x0 0x10>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -523,7 +523,7 @@
reg = <0x0 0xff1b0010 0x0 0x10>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -534,7 +534,7 @@
reg = <0x0 0xff1b0020 0x0 0x10>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -546,7 +546,7 @@
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwmir_pin>;
#pwm-cells = <3>;
status = "disabled";

View File

@@ -848,7 +848,7 @@
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
@@ -859,7 +859,7 @@
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
@@ -879,7 +879,7 @@
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";

View File

@@ -1255,7 +1255,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@@ -1266,7 +1266,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@@ -1277,7 +1277,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@@ -1288,7 +1288,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3a_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@@ -1814,7 +1814,7 @@
compatible = "rockchip,vop-pwm";
reg = <0x0 0xff8f01a0 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&vop1_pwm_pin>;
clocks = <&cru SCLK_VOP1_PWM>;
clock-names = "pwm";
@@ -1883,7 +1883,7 @@
compatible = "rockchip,vop-pwm";
reg = <0x0 0xff9001a0 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&vop0_pwm_pin>;
clocks = <&cru SCLK_VOP0_PWM>;
clock-names = "pwm";

View File

@@ -14,6 +14,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/time.h>
@@ -36,6 +37,8 @@ struct rockchip_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
struct clk *pclk;
struct pinctrl *pinctrl;
struct pinctrl_state *active_state;
const struct rockchip_pwm_data *data;
void __iomem *base;
bool vop_pwm_en; /* indicate voppwm mirror register state */
@@ -105,7 +108,7 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip,
}
static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_state *state)
struct pwm_state *state)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
unsigned long period, duty;
@@ -237,6 +240,8 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
*/
rockchip_pwm_get_state(chip, pwm, state);
if (state->enabled)
ret = pinctrl_select_state(pc->pinctrl, pc->active_state);
out:
clk_disable(pc->pclk);
@@ -380,6 +385,18 @@ static int rockchip_pwm_probe(struct platform_device *pdev)
goto err_clk;
}
pc->pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(pc->pinctrl)) {
dev_err(&pdev->dev, "Get pinctrl failed!\n");
return PTR_ERR(pc->pinctrl);
}
pc->active_state = pinctrl_lookup_state(pc->pinctrl, "active");
if (IS_ERR(pc->active_state)) {
dev_err(&pdev->dev, "No active pinctrl state\n");
return PTR_ERR(pc->active_state);
}
platform_set_drvdata(pdev, pc);
pc->data = id->data;