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phy: rockchip-snps-pcie3: Configure registers only when defining phy mode

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Change-Id: I75ef3313d59708f9238dbb7cac3a7f210fb97c9b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2024-12-17 22:38:58 +08:00
parent a437e6a016
commit 058b229588
1 changed files with 7 additions and 9 deletions
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16
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -276,17 +276,15 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
if (!ret)
if (!ret) {
priv->pcie30_phymode = val;
else
if (priv->pcie30_phymode > 4)
priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
(0x7<<16) | priv->pcie30_phymode);
} else {
priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
/* Select correct pcie30_phymode */
if (priv->pcie30_phymode > 4)
priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
(0x7<<16) | priv->pcie30_phymode);
}
/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
if (!IS_ERR(priv->pipe_grf)) {