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arm64: dts: rockchip: rk3588-vehicle-evb: init v23 dts files
Signed-off-by: Luo Wei <lw@rock-chips.com> Signed-off-by: Cai Wenzhong <cwz@rock-chips.com> Signed-off-by: Xu Xuehui <xxh@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com> Change-Id: Id704f2ee9a4f1c117cad6ae63f2d71f93c9dcc12
This commit is contained in:
Luo Wei
@@ -323,6 +323,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v20.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v21.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v22.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v23.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-s66-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10-linux.dtb
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@@ -0,0 +1,726 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/display/media-bus-format.h>
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/ {
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max96712_dphy3_osc: max96712-dphy3-oscillator {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96712-dphy3-osc";
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};
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max96712_dphy3_vcc1v2: max96712-dphy3-vcc1v2 {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_vcc1v2";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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startup-delay-us = <850>;
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vin-supply = <&vcc5v0_sys>;
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};
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max96712_dphy3_vcc1v8: max96712-dphy3-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_vcc1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <200>;
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vin-supply = <&vcc_3v3_s3>;
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};
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max96712_dphy3_pwdn_regulator: max96712-dphy3-pwdn-regulator {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_pwdn";
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gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dphy3_pwdn>;
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enable-active-high;
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startup-delay-us = <10000>;
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off-on-delay-us = <5000>;
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vin-supply = <&max96712_dphy3_vcc1v8>;
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};
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max96712_dphy3_poc_regulator: max96712-dphy3-poc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "max96712_dphy3_poc";
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gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <10000>;
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off-on-delay-us = <5000>;
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vin-supply = <&vcc12v_dcin>;
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};
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};
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&csi2_dphy1_hw {
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status = "okay";
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};
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&csi2_dphy3 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy3_in_max96712: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96712_dphy3_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy3_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi4_csi2_input>;
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};
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};
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};
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};
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&i2c6 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6m3_xfer>;
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max96712_dphy3: max96712@29 {
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compatible = "maxim4c,max96712";
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status = "okay";
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reg = <0x29>;
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clock-names = "xvclk";
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clocks = <&max96712_dphy3_osc 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dphy3_errb>, <&max96712_dphy3_lock>;
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power-domains = <&power RK3588_PD_VI>;
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rockchip,grf = <&sys_grf>;
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vcc1v2-supply = <&max96712_dphy3_vcc1v2>;
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vcc1v8-supply = <&max96712_dphy3_vcc1v8>;
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pwdn-supply = <&max96712_dphy3_pwdn_regulator>;
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lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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port {
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max96712_dphy3_out: endpoint {
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remote-endpoint = <&mipi_dphy3_in_max96712>;
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data-lanes = <1 2 3 4>;
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};
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};
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/* support mode config start */
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support-mode-config {
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status = "okay";
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bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
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sensor-width = <1920>;
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sensor-height = <1281>;
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crop-rect = <0 1 1920 1280>; // [ left, top, width, height ]
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max-fps-numerator = <10000>;
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max-fps-denominator = <300000>;
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bpp = <16>;
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link-freq-idx = <20>;
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};
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/* support mode config end */
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/* serdes local device start */
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serdes-local-device {
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status = "okay";
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/* GMSL LINK config start */
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gmsl-links {
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status = "okay";
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link-vdd-ldo1-en = <1>;
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link-vdd-ldo2-en = <1>;
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// Link A: link-id = 0
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gmsl-link-config-0 {
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status = "okay";
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link-id = <0>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy3_cam0>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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14 D1 03 00 00 // VGAHiGain
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14 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link B: link-id = 1
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gmsl-link-config-1 {
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status = "okay";
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link-id = <1>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy3_cam1>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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15 D1 03 00 00 // VGAHiGain
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15 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link C: link-id = 2
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gmsl-link-config-2 {
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status = "okay";
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link-id = <2>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy3_cam2>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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16 D1 03 00 00 // VGAHiGain
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16 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link D: link-id = 3
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gmsl-link-config-3 {
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status = "okay";
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link-id = <3>; // Link ID: 0/1/2/3
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link-type = <1>; // 0: GMSL1, 1: GMSL2
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link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
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link-tx-rate = <0>; // 0: default for 187.5MBPS
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link-remote-cam = <&max96712_dphy3_cam3>; // remote camera
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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17 D1 03 00 00 // VGAHiGain
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17 45 00 00 00 // Disable SSC
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];
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};
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};
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};
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/* GMSL LINK config end */
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/* VIDEO PIPE config start */
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video-pipes {
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status = "okay";
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// Video Pipe 0
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video-pipe-config-0 {
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status = "okay";
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pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <0>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
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09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
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09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
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09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 12 01 00 00 // DST2 VC = 0, DT = Frame End
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];
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};
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};
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// Video Pipe 1
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video-pipe-config-1 {
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status = "okay";
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pipe-id = <1>; // Video Pipe 1: pipe-id = 1
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <1>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
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09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
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09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
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09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 52 41 00 00 // DST2 VC = 1, DT = Frame End
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];
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};
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};
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// Video Pipe 2
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video-pipe-config-2 {
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status = "okay";
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pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <2>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
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09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
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09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
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09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 92 81 00 00 // DST2 VC = 2, DT = Frame End
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];
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};
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};
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// Video Pipe 3
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video-pipe-config-3 {
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status = "okay";
|
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pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <3>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
|
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
|
||||
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
|
||||
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
|
||||
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
/* VIDEO PIPE config end */
|
||||
|
||||
/* MIPI TXPHY config start */
|
||||
mipi-txphys {
|
||||
status = "okay";
|
||||
|
||||
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
|
||||
phy-force-clock-out = <1>; // 1: default for force clock out
|
||||
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
|
||||
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
|
||||
|
||||
// MIPI TXPHY A: phy-id = 0
|
||||
mipi-txphy-config-0 {
|
||||
status = "okay";
|
||||
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
|
||||
|
||||
phy-type = <0>; // 0: DPHY, 1: CPHY
|
||||
auto-deskew = <0x80>;
|
||||
data-lane-num = <4>;
|
||||
data-lane-map = <0x4>;
|
||||
vc-ext-en = <0>;
|
||||
};
|
||||
|
||||
// MIPI TXPHY B: phy-id = 1
|
||||
mipi-txphy-config-1 {
|
||||
status = "okay";
|
||||
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
|
||||
|
||||
phy-type = <0>; // 0: DPHY, 1: CPHY
|
||||
auto-deskew = <0x80>;
|
||||
data-lane-num = <4>;
|
||||
data-lane-map = <0xe>;
|
||||
vc-ext-en = <0>;
|
||||
};
|
||||
};
|
||||
/* MIPI TXPHY config end */
|
||||
|
||||
/* local device extra init sequence */
|
||||
extra-init-sequence {
|
||||
status = "okay";
|
||||
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// common init sequence such as fsync / gpio and so on
|
||||
04 A2 00 00 00 // Master link Video 0 for frame sync generation
|
||||
04 AA 00 00 00 // Disable Vsync-Fsync overlap window
|
||||
04 AB 00 00 00 // Disable Vsync-Fsync overlap window
|
||||
04 A8 00 00 00 // FRM_DIFF_ERR_THR_L
|
||||
04 A9 00 00 00 // FRM_DIFF_ERR_THR_H
|
||||
04 A7 0c 00 00 // FSYNC_PERIOD_H, Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz
|
||||
04 A6 bf 00 00 // FSYNC_PERIOD_M
|
||||
04 A5 35 00 00 // FSYNC_PERIOD_L
|
||||
04 AF c0 00 00 // FSYNC is GMSL2 type, use osc for fsync
|
||||
04 B1 40 00 00 // FSYNC_TX_ID: set 8 to match MFP8 on serializer side
|
||||
04 A0 04 00 00 // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode
|
||||
];
|
||||
};
|
||||
};
|
||||
/* serdes local device end */
|
||||
|
||||
/* i2c-mux start */
|
||||
i2c-mux {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy3_ser0: max96717@41 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x41>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy3_cam0: isx021@31 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x31>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy3_ser0>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy3_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy3_cam0_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy3_ser1: max96717@42 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x42>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy3_cam1: isx021@32 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x32>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy3_ser1>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy3_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <1>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy3_cam1_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy3_ser2: max96717@43 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x43>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy3_cam2: isx021@33 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x33>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy3_ser2>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy3_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <2>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy3_cam2_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy3_ser3: max96717@44 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x44>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy3_cam3: isx021@34 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x34>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy3_ser3>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy3_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <3>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy3_cam3_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
};
|
||||
/* i2c-mux end */
|
||||
};
|
||||
};
|
||||
|
||||
&mipi4_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi4_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi4_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi4_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds4 {
|
||||
status = "okay";
|
||||
/* parameters for do cif reset detecting:
|
||||
* index0: monitor mode,
|
||||
0 for idle,
|
||||
1 for continue,
|
||||
2 for trigger,
|
||||
3 for hotplug (for nextchip)
|
||||
* index1: the frame id to start timer,
|
||||
min is 2
|
||||
* index2: frame num of monitoring cycle
|
||||
* index3: err time for keep monitoring
|
||||
after finding out err (ms)
|
||||
* index4: csi2 err reference val for resetting
|
||||
*/
|
||||
rockchip,cif-monitor = <3 2 1 1000 5>;
|
||||
|
||||
port {
|
||||
cif_mipi4_in: endpoint {
|
||||
remote-endpoint = <&mipi4_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
rockchip,android-usb-camerahal-enable;
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
max96712-dphy3 {
|
||||
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
|
||||
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
max96712_dphy3_errb: max96712-dphy3-errb {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
max96712_dphy3_lock: max96712-dphy3-lock {
|
||||
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
};
|
||||
120
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi
Normal file
120
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23-audio.dtsi
Normal file
@@ -0,0 +1,120 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
/delete-node/ car-rk3308-sound;
|
||||
|
||||
dummy_codec: dummy-codec {
|
||||
compatible = "rockchip,dummy-codec";
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sound0 {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,tdm";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,bitclock-master = <&codec_master>;
|
||||
simple-audio-card,frame-master = <&codec_master>;
|
||||
status = "okay";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
codec_master: simple-audio-card,codec {
|
||||
sound-dai = <&dummy_codec>;
|
||||
};
|
||||
};
|
||||
|
||||
bt_codec: bt-codec {
|
||||
compatible = "delta,dfbmcs320";
|
||||
#sound-dai-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sound1 {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,bt";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s2_2ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&bt_codec 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2s1_8ch {
|
||||
pinctrl-0 = <&i2s1m0_lrck_rx
|
||||
&i2s1m0_lrck_tx
|
||||
&i2s1m0_sclk_rx
|
||||
&i2s1m0_sclk_tx
|
||||
&i2s1m0_sdi0
|
||||
&i2s1m0_sdi1
|
||||
&i2s1m0_sdo0
|
||||
&i2s1m0_sdo1
|
||||
&i2s1m0_sdo2
|
||||
&gpio_fsxn_pins>;
|
||||
fsxn-rx-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
fsxn-tx-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,tdm-multi-lanes;
|
||||
rockchip,tdm-tx-lanes = <3>;
|
||||
rockchip,tdm-rx-lanes = <2>;
|
||||
/delete-property/ rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2_2ch {
|
||||
pinctrl-0 = <&i2s2m1_lrck
|
||||
&i2s2m1_sclk
|
||||
&i2s2m1_sdi
|
||||
&i2s2m1_sdo>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
i2s1_rx_tx {
|
||||
i2s1m0_lrck_rx: i2s1m0-lrck-rx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrck_rx */
|
||||
<4 RK_PA4 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2s1m0_lrck_tx: i2s1m0-lrck-tx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrck_tx */
|
||||
<4 RK_PA2 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2s1m0_sclk_rx: i2s1m0-sclk-rx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclk_rx */
|
||||
<4 RK_PA3 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2s1m0_sclk_tx: i2s1m0-sclk-tx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclk_tx */
|
||||
<4 RK_PA1 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
fsxn {
|
||||
/omit-if-no-ref/
|
||||
gpio_fsxn_pins: gpio-fsxn-pins {
|
||||
rockchip,pins =
|
||||
<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
643
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts
Normal file
643
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts
Normal file
@@ -0,0 +1,643 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3588-vehicle-evb-v21.dtsi"
|
||||
#include "rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi"
|
||||
#include "rk3588-vehicle-evb-maxim-max96712-dphy3-isx021.dtsi"
|
||||
#include "rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi"
|
||||
#include "rk3588-vehicle-serdes-mfd-display-maxim.dtsi"
|
||||
#include "rk3588-vehicle-evb-v23-audio.dtsi"
|
||||
#include "rk3588-android.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3588 VEHICLE EVB V23 Board";
|
||||
compatible = "rockchip,rk3588-vehicle-evb-v23", "rockchip,rk3588";
|
||||
|
||||
vcc5v0_buck: vcc5v0-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_buck_en>;
|
||||
startup-delay-us = <2500>;
|
||||
off-on-delay-us = <1500>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
#if 0
|
||||
vcc4v0_sys_mode: vcc4v0-sys-mode {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc4v0_sys_mode";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <4000000>;
|
||||
regulator-max-microvolt = <4000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc4v0_sys_mode_en>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <4000000>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
lcd1_vcc12v_buck: lcd1_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd1_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd2_vcc12v_buck: lcd2_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd2_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd3_vcc12v_buck: lcd3_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd3_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd4_vcc12v_buck: lcd4_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd4_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd5_vcc12v_buck: lcd5_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd5_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd6_vcc12v_buck: lcd6_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd6_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck: dcphy0_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy1_vcc12v_buck: dcphy1_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy1_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck: dphy0_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck: dphy3_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 9 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0_host_usb20: vcc5v0-host-usb20 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg_usb20";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
//enable-active-high;
|
||||
gpio = <&nca9539_gpio 10 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_host_usb30: vcc5v0-host-usb30 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host_usb30";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 11 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
adsp_vcc12v_buck: adsp_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "adsp_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 12 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
minipcie_power_buck: minipcie_power-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "minipcie_power_buck";
|
||||
regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&nca9539_gpio 13 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vehicle_dummy: vehicle_dummy {
|
||||
status = "okay";
|
||||
compatible = "rockchip,vehicle-dummy-gpio";
|
||||
reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie_wifi: vcc3v3-pcie-wifi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie_wifi";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
wireless_bluetooth: wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
clocks = <&hym8563>;
|
||||
clock-names = "ext_clock";
|
||||
uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
|
||||
pinctrl-1 = <&uart7_gpios>;
|
||||
BT,reset_gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless_wlan: wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
wifi_chip_type = "ap6398s";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus
|
||||
&phydisb>;
|
||||
tx_delay = <0x20>;
|
||||
phy-handle = <&rgmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
rgmii_vddio = "1v8";
|
||||
};
|
||||
};
|
||||
|
||||
&hym8563 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&max96712_dphy3_vcc1v2 {
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
};
|
||||
|
||||
&max96712_dphy3_pwdn_regulator {
|
||||
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&max96712_dphy3_poc_regulator {
|
||||
vin-supply = <&dphy3_vcc12v_buck>;
|
||||
gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&max96712_dphy3 {
|
||||
lock-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&max96756_dphy0_vcc1v2 {
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
};
|
||||
|
||||
&avdd1v8_ddr_pll_s0 {
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
himax@45 {
|
||||
himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
himax_split@46 {
|
||||
himax,irq-gpio = <&gpio3 RK_PB0 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
/*dsi0*/
|
||||
&i2c2_max96789 {
|
||||
route-enable;
|
||||
};
|
||||
|
||||
&i2c2_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd1_vcc12v_buck>;
|
||||
};
|
||||
|
||||
&i2c2_max96752_split {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd2_vcc12v_buck>;
|
||||
};
|
||||
|
||||
/*dp0*/
|
||||
&i2c4 {
|
||||
himax@45 {
|
||||
himax,irq-gpio = <&gpio3 RK_PD5 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "sii,s35390a";
|
||||
reg = <0x30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&s35390a_int>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4_max96745 {
|
||||
//use-delay-work;
|
||||
};
|
||||
|
||||
&i2c4_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd5_vcc12v_buck>;
|
||||
|
||||
himax@45 {
|
||||
himax,irq-gpio = <&gpio3 RK_PD5 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
/*edp0*/
|
||||
&i2c5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5m0_xfer>;
|
||||
|
||||
ilitek@41 {
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5_max96745 {
|
||||
//use-delay-work;
|
||||
};
|
||||
|
||||
&i2c5_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd3_vcc12v_buck>;
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6m1_xfer>;
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-names = "init";
|
||||
pinctrl-0 = <&max96712_dphy3_pwdn
|
||||
&max96712_dphy3_errb
|
||||
&max96712_dphy3_lock>;
|
||||
|
||||
|
||||
gmac0 {
|
||||
phydisb: phydisb {
|
||||
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
max96712-dphy3 {
|
||||
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
|
||||
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
max96712_dphy3_errb: max96712-dphy3-errb {
|
||||
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
max96712_dphy3_lock: max96712-dphy3-lock {
|
||||
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
s35390a {
|
||||
s35390a_int: s35390a-int {
|
||||
rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
touch {
|
||||
//dsi0-i2c2
|
||||
touch_gpio_dsi0: touch-gpio-dsi0 {
|
||||
rockchip,pins =
|
||||
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //RST->V22 INT
|
||||
};
|
||||
//dsi1-i2c6
|
||||
touch_gpio_dsi1: touch-gpio-dsi1 {
|
||||
rockchip,pins =
|
||||
<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //INT
|
||||
};
|
||||
//dp0-i2c4
|
||||
touch_gpio_dp0: touch-gpio-dp0 {
|
||||
rockchip,pins =
|
||||
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
//edp0-i2c5
|
||||
touch_gpio_edp0: touch-gpio-edp0 {
|
||||
rockchip,pins =
|
||||
<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; //INT
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0-buck {
|
||||
vcc5v0_buck_en: vcc5v0-buck-en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
#if 0
|
||||
vcc4v0-mode {
|
||||
vcc4v0_sys_mode_en: vcc4v0-sys-mode-en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
wireless-bluetooth {
|
||||
uart7_gpios: uart7-gpios {
|
||||
rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
bt_reset_gpio: bt-reset-gpio {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
bt_wake_gpio: bt-wake-gpio {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
bt_irq_gpio: bt-irq-gpio {
|
||||
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rockchip_suspend {
|
||||
rockchip,sleep-mode-config = <
|
||||
(0
|
||||
| RKPM_SLP_ARMOFF_DDRPD
|
||||
| RKPM_SLP_PMU_PMUALIVE_32K
|
||||
| RKPM_SLP_PMU_DIS_OSC
|
||||
| RKPM_SLP_32K_EXT
|
||||
)
|
||||
>;
|
||||
rockchip,wakeup-config = <
|
||||
(0
|
||||
| RKPM_CPU0_WKUP_EN
|
||||
| RKPM_GPIO_WKUP_EN
|
||||
)
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
//phy-supply = <&vcc5v0_host_usb20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host_usb30>;
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
phy-supply = <&vcc5v0_host_usb30>;
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host_usb30>;
|
||||
};
|
||||
|
||||
&vdd_log_s0 {
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc_3v3_s0 {
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc_1v8_s0 {
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&vdd_1v8_pll_s0 {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
&vcc5v0_host {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "disabled";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user