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phy/rockchip: typec: PLL1 settings improvements

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When I tested DP function on excavator, I found that commit 1bf7191033de
("BACKPORT: FROMLIST: phy: rockchip-typec: support variable phy config value"),
which change pll settings, but it does not work as expected on excavator board.
With this patch series, DP works well on excavator and roc.

Change-Id: I48fe0c51e322369d1aff352f4ebaf1096f264834
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2018-08-03 17:25:06 +08:00
committed by Tao Huang
parent f0f004d826
commit 08aea10ffd
1 changed files with 21 additions and 21 deletions
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42
drivers/phy/rockchip/phy-rockchip-typec.c
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@@ -367,7 +367,7 @@ struct phy_reg {
u32 addr;
};
struct phy_reg usb3_pll_cfg[] = {
static const struct phy_reg usb3_pll_cfg[] = {
{ 0xf0, CMN_PLL0_VCOCAL_INIT },
{ 0x18, CMN_PLL0_VCOCAL_ITER },
{ 0xd0, CMN_PLL0_INTDIV },
@@ -384,15 +384,15 @@ struct phy_reg usb3_pll_cfg[] = {
{ 0x8, CMN_DIAG_PLL0_LF_PROG },
};
struct phy_reg dp_pll_rbr_cfg[] = {
static const struct phy_reg dp_pll_rbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b9, CMN_PLL1_VCOCAL_START },
{ 0x87, CMN_PLL1_INTDIV },
{ 0, CMN_PLL1_FRACDIV },
{ 0x22, CMN_PLL1_HIGH_THR },
{ 0x8000, CMN_PLL1_SS_CTRL1 },
{ 0, CMN_PLL1_SS_CTRL2 },
{ 0x0086, CMN_PLL1_INTDIV },
{ 0xf915, CMN_PLL1_FRACDIV },
{ 0x0022, CMN_PLL1_HIGH_THR },
{ 0x0140, CMN_PLL1_SS_CTRL1 },
{ 0x7f03, CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0, CMN_PLLSM1_USER_DEF_CTRL },
{ 0, CMN_DIAG_PLL1_OVRD },
@@ -406,15 +406,15 @@ struct phy_reg dp_pll_rbr_cfg[] = {
{ 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
};
struct phy_reg dp_pll_hbr_cfg[] = {
static const struct phy_reg dp_pll_hbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b4, CMN_PLL1_VCOCAL_START },
{ 0xe1, CMN_PLL1_INTDIV },
{ 0, CMN_PLL1_FRACDIV },
{ 0x5, CMN_PLL1_HIGH_THR },
{ 0x8000, CMN_PLL1_SS_CTRL1 },
{ 0, CMN_PLL1_SS_CTRL2 },
{ 0x00e0, CMN_PLL1_INTDIV },
{ 0xf479, CMN_PLL1_FRACDIV },
{ 0x0038, CMN_PLL1_HIGH_THR },
{ 0x0204, CMN_PLL1_SS_CTRL1 },
{ 0x7f03, CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
{ 0, CMN_DIAG_PLL1_OVRD },
@@ -428,15 +428,15 @@ struct phy_reg dp_pll_hbr_cfg[] = {
{ 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
};
struct phy_reg dp_pll_hbr2_cfg[] = {
static const struct phy_reg dp_pll_hbr2_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b4, CMN_PLL1_VCOCAL_START },
{ 0xe1, CMN_PLL1_INTDIV },
{ 0, CMN_PLL1_FRACDIV },
{ 0x5, CMN_PLL1_HIGH_THR },
{ 0x8000, CMN_PLL1_SS_CTRL1 },
{ 0, CMN_PLL1_SS_CTRL2 },
{ 0x00e0, CMN_PLL1_INTDIV },
{ 0xf479, CMN_PLL1_FRACDIV },
{ 0x0038, CMN_PLL1_HIGH_THR },
{ 0x0204, CMN_PLL1_SS_CTRL1 },
{ 0x7f03, CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
{ 0, CMN_DIAG_PLL1_OVRD },
@@ -505,7 +505,7 @@ static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy *tcphy)
static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy, int link_rate)
{
struct phy_reg *phy_cfg;
const struct phy_reg *phy_cfg;
u32 clk_ctrl;
u32 i, cfg_size, hsclk_sel;
@@ -595,7 +595,7 @@ static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, int link_rate,
val = val & 0x8fff;
switch (link_rate) {
case 540000:
val |= (4 << 12);
val |= (5 << 12);
break;
case 162000:
case 270000: