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amvecm: fix hdr no effect

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PD#151008: fix hdr no effect

Change-Id: I9edc076cb74783d26e1f16ebeaceb48dbb7e6bfe
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>
This commit is contained in:
MingLiang Dong
2017-09-21 16:26:47 +08:00
committed by Jianxin Pan
parent 0385280d28
commit 0a19c008ff
11 changed files with 3125 additions and 674 deletions
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11
drivers/amlogic/media/enhancement/amvecm/amcm.c
View File

@@ -148,6 +148,15 @@ void am_set_regmap(struct am_regs_s *p)
__func__, p->am_reg[i].addr);
break;
}
if (!cm_en) {
if (p->am_reg[i].addr == 0x208)
p->am_reg[i].val =
p->am_reg[i].val & 0xfffffffd;
pr_amcm_dbg("[amcm]:%s REG_TYPE_INDEX_VPPCHROMA addr:0x%x",
__func__, p->am_reg[i].addr);
}
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
p->am_reg[i].addr);
if (p->am_reg[i].mask == 0xffffffff)
@@ -221,6 +230,7 @@ void am_set_regmap(struct am_regs_s *p)
break;
}
}
return;
}
void amcm_disable(void)
@@ -363,6 +373,7 @@ void cm_latch_process(void)
} else if ((cm_en == 0) && (cm_level_last != 0xff)) {
cm_level_last = 0xff;
amcm_disable();/* CM manage disable */
pr_amcm_dbg("\n[amcm..] set cm disable!!!\n");
}
}

1719
drivers/amlogic/media/enhancement/amvecm/amcsc.c
View File

File diff suppressed because it is too large Load Diff

19
drivers/amlogic/media/enhancement/amvecm/amcsc.h
View File

@@ -94,6 +94,20 @@ struct matrix_s {
u16 right_shift;
};
enum mtx_en_e {
POST_MTX_EN = 0,
VD2_MTX_EN = 4,
VD1_MTX_EN,
XVY_MTX_EN,
OSD1_MTX_EN
};
#define POST_MTX_EN_MASK (1 << POST_MTX_EN)
#define VD2_MTX_EN_MASK (1 << VD2_MTX_EN)
#define VD1_MTX_EN_MASK (1 << VD1_MTX_EN)
#define XVY_MTX_EN_MASK (1 << XVY_MTX_EN)
#define OSD1_MTX_EN_MASK (1 << OSD1_MTX_EN)
#define LUT_289_SIZE 289
extern unsigned int lut_289_mapping[LUT_289_SIZE];
extern int dnlp_en;
@@ -106,7 +120,8 @@ extern uint sdr_mode;
extern uint hdr_flag;
extern int video_rgb_ogo_xvy_mtx_latch;
extern void amvecm_matrix_process(struct vframe_s *vf);
extern int amvecm_matrix_process(
struct vframe_s *vf, struct vframe_s *vf_rpt, int flags);
extern int amvecm_hdr_dbg(u32 sel);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
@@ -119,5 +134,7 @@ extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
extern u32 get_video_enabled(void);
#endif /* AM_CSC_H */

343
drivers/amlogic/media/enhancement/amvecm/amve.c
View File

@@ -19,6 +19,7 @@
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
/* #include <mach/am_regs.h> */
#include <linux/amlogic/media/utils/amstream.h>
#include <linux/amlogic/media/amvecm/ve.h>
@@ -55,7 +56,7 @@ unsigned long flags;
#define NEW_DNLP_IN_SHARPNESS 2
#define NEW_DNLP_IN_VPP 1
unsigned int dnlp_sel = NEW_DNLP_IN_VPP;
unsigned int dnlp_sel = NEW_DNLP_IN_SHARPNESS;
module_param(dnlp_sel, int, 0664);
MODULE_PARM_DESC(dnlp_sel, "dnlp_sel");
/* #endif */
@@ -147,6 +148,42 @@ MODULE_PARM_DESC(ve_dnlp_ankle, "ve_dnlp_ankle");
module_param(ve_dnlp_strength, int, 0664);
MODULE_PARM_DESC(ve_dnlp_strength, "ve_dnlp_strength");
/*static int debug_add_curve_en;*/
int glb_scurve[65];
int glb_clash_curve[65];
/*static int glb_scurve_bld_rate;*/
/*static int glb_clash_curve_bld_rate;*/
int glb_pst_gamma[65];
/*static int glb_pst_gamma_bld_rate;*/
static int debug_add_curve_en;
module_param(debug_add_curve_en, int, 0664);
MODULE_PARM_DESC(debug_add_curve_en, "debug_add_curve_en");
static int ve_usr_defined_test_s_mode;
module_param(ve_usr_defined_test_s_mode, int, 0664);
MODULE_PARM_DESC(ve_usr_defined_test_s_mode, "ve_usr_defined_test_s_mode");
static int ve_usr_defined_test_c_mode;
module_param(ve_usr_defined_test_c_mode, int, 0664);
MODULE_PARM_DESC(ve_usr_defined_test_c_mode, "ve_usr_defined_test_c_mode");
static int ve_usr_defined_test_g_mode;
module_param(ve_usr_defined_test_g_mode, int, 0664);
MODULE_PARM_DESC(ve_usr_defined_test_g_mode, "ve_usr_defined_test_g_mode");
static int glb_scurve_bld_rate;
module_param(glb_scurve_bld_rate, int, 0664);
MODULE_PARM_DESC(glb_scurve_bld_rate, "glb_scurve_bld_rate");
static int glb_clash_curve_bld_rate;
module_param(glb_clash_curve_bld_rate, int, 0664);
MODULE_PARM_DESC(glb_clash_curve_bld_rate, "glb_clash_curve_bld_rate");
static int glb_pst_gamma_bld_rate;
module_param(glb_pst_gamma_bld_rate, int, 0664);
MODULE_PARM_DESC(glb_pst_gamma_bld_rate, "glb_pst_gamma_bld_rate");
static int dnlp_respond;
module_param(dnlp_respond, int, 0664);
MODULE_PARM_DESC(dnlp_respond, "dnlp_respond");
@@ -209,7 +246,7 @@ module_param(video_rgb_ogo_mode_sw, int, 0664);
MODULE_PARM_DESC(video_rgb_ogo_mode_sw,
"enable/disable video_rgb_ogo_mode_sw");
static int video_rgb_ogo_xvy_mtx = 1;
int video_rgb_ogo_xvy_mtx;
module_param(video_rgb_ogo_xvy_mtx, int, 0664);
MODULE_PARM_DESC(video_rgb_ogo_xvy_mtx,
"enable/disable video_rgb_ogo_xvy_mtx");
@@ -680,22 +717,15 @@ static unsigned int assist_cnt;/* ASSIST_SPARE8_REG1; */
static unsigned int assist_cnt2;/* ASSIST_SPARE8_REG2; */
/* video lock */
#define VLOCK_MODE_ENC 0
#define VLOCK_MODE_PLL 1
#define VLOCK_MODE_MANUAL_PLL 2
#define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/
/* 0:enc;1:pll;2:manual pll */
static unsigned int vlock_mode = VLOCK_MODE_MANUAL_PLL;
static unsigned int vlock_en = 1;
unsigned int vlock_mode = VLOCK_MODE_MANUAL_PLL;
unsigned int vlock_en = 1;
/*0:only support 50->50;60->60;24->24;30->30;*/
/*1:support 24/30/50/60/100/120 mix,such as 50->60;*/
static unsigned int vlock_adapt;
static unsigned int vlock_dis_cnt_limit = 2;
/*4k@60hz test case: delta 200 is close to 500K*/
static unsigned int vlock_delta_limit_frac = 100;
static unsigned int vlock_delta_limit_m;
static unsigned int vlock_delta_limit = 2;
/*vlock_debug:bit0:disable info;bit1:format change info;bit2:force reset*/
static unsigned int vlock_debug;
static unsigned int vlock_dynamic_adjust = 1;
@@ -714,10 +744,39 @@ static char pre_vout_mode[64];
static bool vlock_vmode_changed;
static unsigned int pre_hiu_reg_m;
static unsigned int pre_hiu_reg_frac;
static unsigned int vlock_dis_cnt_step1;
static unsigned int vlock_dis_cnt_step1_limit = 300;
static unsigned int vlock_en_cnt_step1_limit = 300;
static unsigned int vlock_dis_cnt_no_vf;
static unsigned int vlock_dis_cnt_no_vf_limit = 5;
static unsigned int vlock_log_cnt;/*cnt base: vlock_log_s*/
static unsigned int vlock_log_size = 60;/*size base: vlock_log_s*/
static unsigned int vlock_log_delta_frac = 100;
static unsigned int vlock_log_delta_ivcnt = 0xff;
static unsigned int vlock_log_delta_ovcnt = 0xff;
static unsigned int vlock_log_delta_vcnt = 0xff;
static unsigned int vlock_log_last_ivcnt;
static unsigned int vlock_log_last_ovcnt;
static unsigned int vlock_log_delta_m;
static unsigned int vlock_log_delta_en;
module_param(vlock_log_size, uint, 0664);
MODULE_PARM_DESC(vlock_log_size, "\n vlock_log_size\n");
module_param(vlock_log_cnt, uint, 0664);
MODULE_PARM_DESC(vlock_log_cnt, "\n vlock_log_cnt\n");
module_param(vlock_log_delta_frac, uint, 0664);
MODULE_PARM_DESC(vlock_log_delta_frac, "\n vlock_log_delta_frac\n");
module_param(vlock_log_delta_m, uint, 0664);
MODULE_PARM_DESC(vlock_log_delta_m, "\n vlock_log_delta_m\n");
module_param(vlock_log_delta_en, uint, 0664);
MODULE_PARM_DESC(vlock_log_delta_en, "\n vlock_log_delta_en\n");
module_param(vlock_log_delta_ivcnt, uint, 0664);
MODULE_PARM_DESC(vlock_log_delta_ivcnt, "\n vlock_log_delta_ivcnt\n");
module_param(vlock_log_delta_ovcnt, uint, 0664);
MODULE_PARM_DESC(vlock_log_delta_ovcnt, "\n vlock_log_delta_ovcnt\n");
module_param(vlock_log_delta_vcnt, uint, 0664);
MODULE_PARM_DESC(vlock_log_delta_vcnt, "\n vlock_log_delta_vcnt\n");
static unsigned int vlock_log_en;
/* 3d sync parts begin */
unsigned int sync_3d_h_start;
unsigned int sync_3d_h_end;
@@ -1730,10 +1789,19 @@ void clash_fun(unsigned int *oMap, unsigned int *iHst,
oMap[i+1] = j + (hstBgn << 4);
}
if (debug_add_curve_en) {
for (i = 0; i < 65; i++) {
oMap[i] = ((128 - glb_clash_curve_bld_rate) * oMap[i] +
glb_clash_curve_bld_rate * (glb_clash_curve[i] << 2) +
64) >> 7;
}
}
if (prt_flg)
for (i = hstBgn; i < hstEnd; i++)
pr_info("#CL: [%02d: %5d]: %4d => %4d]\n",
i, iHst[i], i<<4, oMap[i]);
i, iHst[i], i << 4, oMap[i]);
}
/*xhu*/
@@ -2257,6 +2325,11 @@ static void dnlp_gmma_cuvs(unsigned int gmma_rate,
nTmp = (nTmp*(64 - hgh_alpha) +
(hgh_alpha*i<<4) + 8)>>4;
if (debug_add_curve_en) {
nTmp = ((128 - glb_scurve_bld_rate) * nTmp +
glb_scurve_bld_rate * (glb_scurve[i] << 4) + 64) >> 7;
}
if (nTmp < 0)
nTmp = 0;
else if (nTmp > 4095)
@@ -2340,6 +2413,13 @@ static void dnlp_blkgma_bld(unsigned int *blk_gma_rat)
nTmp0 = (nTmp0+32)>>6; /* 0~1024 */
blk_gma_bld[i] = nTmp0;
if (debug_add_curve_en) {
blk_gma_bld[i] =
((128 - glb_pst_gamma_bld_rate) * blk_gma_bld[i] +
glb_pst_gamma_bld_rate *
(glb_pst_gamma[i] << 2) + 64) >> 7;
}
if ((dnlp_printk >> 2) & 0x1)
pr_info("sc%04d, gm%04d * rat%04d => %04d\n",
clsh_scvbld[i], blk_gma_crv[i], nT1, nTmp0);
@@ -3349,6 +3429,7 @@ static void ve_dnlp_calculate_tgtx_new(struct vframe_s *vf)
/* print debug log once */
if (ve_dnlp_ponce == 1 && dnlp_printk)
dnlp_printk = 0;
}
static void ve_dnlp_calculate_tgt(struct vframe_s *vf)
@@ -3660,7 +3741,7 @@ void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask)
spin_unlock_irqrestore(&vpp_lcd_gamma_lock, flags);
}
void init_write_gamma_table(u16 *data, u32 rgb_mask)
void amve_write_gamma_table(u16 *data, u32 rgb_mask)
{
int i;
int cnt = 0;
@@ -4544,14 +4625,20 @@ static unsigned int vlock_check_output_hz(unsigned int sync_duration_num)
}
static void vlock_enable(bool enable)
{
if (is_meson_gxtvbb_cpu() ||
is_meson_gxbb_cpu() || is_meson_txl_cpu()) {
if (vlock_mode == VLOCK_MODE_MANUAL_PLL)
unsigned int tmp_value;
amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &tmp_value);
if (is_meson_gxtvbb_cpu()) {
if (vlock_mode == VLOCK_MODE_MANUAL_PLL) {
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 0, 20, 1);
else
if (is_meson_gxtvbb_cpu() &&
(((tmp_value >> 21) & 0x3) != 2))
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6,
2, 21, 2);
} else
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6,
enable, 20, 1);
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
} else if (is_meson_txl_cpu() || is_meson_txlx_cpu()) {
if (vlock_mode == VLOCK_MODE_MANUAL_PLL)
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL5, 0, 3, 1);
else
@@ -4582,10 +4669,11 @@ static void vlock_setting(struct vframe_s *vf,
/*clear accum0 value*/
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 5, 1);
}
if ((vlock_mode == VLOCK_MODE_PLL) ||
if ((vlock_mode == VLOCK_MODE_AUTO_PLL) ||
(vlock_mode == VLOCK_MODE_MANUAL_PLL)) {
/* av pal in,1080p60 hdmi out as default */
am_set_regmap(&vlock_pll_in50hz_out60hz);
if ((vlock_debug & 0x1000) == 0)
am_set_regmap(&vlock_pll_in50hz_out60hz);
/*set input & output freq*/
/*bit0~7:input freq*/
/*bit8~15:output freq*/
@@ -4604,7 +4692,7 @@ static void vlock_setting(struct vframe_s *vf,
amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &hiu_reg_value);
amvecm_hiu_reg_read(hiu_reg_value_2_addr,
&hiu_reg_value_2);
if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) {
hiu_m_val = hiu_reg_value & 0x1FF;
hiu_frac_val = hiu_reg_value_2 & 0x3FF;
if (hiu_reg_value_2 & 0x800) {
@@ -4701,7 +4789,7 @@ static void vlock_disable_step1(void)
amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value);
m_reg_value = tmp_value & 0xfff;
if ((m_reg_value != pre_hiu_reg_frac) &&
(pre_hiu_reg_frac != 0)) {
(pre_hiu_reg_m != 0)) {
tmp_value = (tmp_value & 0xfffff000) |
(pre_hiu_reg_frac & 0xfff);
amvecm_hiu_reg_write(hiu_reg_addr, tmp_value);
@@ -4715,6 +4803,7 @@ static void vlock_disable_step1(void)
amvecm_hiu_reg_write(HHI_HDMI_PLL_CNTL, tmp_value);
}
vlock_dis_cnt = vlock_dis_cnt_limit;
memset(pre_vout_mode, 0, sizeof(pre_vout_mode));
pre_vmode = VMODE_INIT_NULL;
pre_source_type = VFRAME_SOURCE_TYPE_OTHERS;
pre_source_mode = VFRAME_SOURCE_MODE_OTHERS;
@@ -4725,6 +4814,7 @@ static void vlock_disable_step1(void)
static void vlock_disable_step2(void)
{
unsigned int temp_val;
/* need delay to disable follow regs(vlsi suggest!!!) */
if (vlock_dis_cnt > 0)
vlock_dis_cnt--;
@@ -4739,6 +4829,9 @@ static void vlock_disable_step2(void)
/* disable vid_lock_en */
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 31, 1);
vlock_state = VLOCK_STATE_DISABLE_STEP2_DONE;
amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &temp_val);
if (is_meson_gxtvbb_cpu() && (((temp_val >> 21) & 0x3) != 0))
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 0, 21, 2);
}
}
static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo,
@@ -4763,19 +4856,112 @@ static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo,
vlock_vmode_changed = 0;
vlock_dis_cnt = 0;
vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE;
vlock_log_cnt = 0;
}
#define VLOCK_REG_NUM 33
struct vlock_log_s {
unsigned int pll_m;
unsigned int pll_frac;
unsigned int vlock_regs[VLOCK_REG_NUM];
};
struct vlock_log_s *vlock_log;
void vlock_log_start(void)
{
unsigned int size_mem;
size_mem = vlock_log_size * sizeof(struct vlock_log_s);
vlock_log = kzalloc(size_mem, GFP_KERNEL);
if (vlock_log == NULL) {
kfree(vlock_log);
return;
}
vlock_log_en = 1;
pr_info("%s done\n", __func__);
}
void vlock_log_stop(void)
{
if (vlock_log != NULL)
kfree(vlock_log);
vlock_log_en = 0;
pr_info("%s done\n", __func__);
}
void vlock_log_print(void)
{
unsigned int i, j;
for (i = 0; i < vlock_log_size; i++) {
pr_info("\n*******[%d]pll_m:0x%x,pll_frac:0x%x*******\n",
i, vlock_log[i].pll_m, vlock_log[i].pll_frac);
for (j = 0; j < VLOCK_REG_NUM;) {
if ((j%8 == 0) && ((j + 7) < VLOCK_REG_NUM)) {
pr_info("0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
vlock_log[i].vlock_regs[j],
vlock_log[i].vlock_regs[j+1],
vlock_log[i].vlock_regs[j+2],
vlock_log[i].vlock_regs[j+3],
vlock_log[i].vlock_regs[j+4],
vlock_log[i].vlock_regs[j+5],
vlock_log[i].vlock_regs[j+6],
vlock_log[i].vlock_regs[j+7]);
j += 8;
} else {
pr_info("0x%08x\t",
vlock_log[i].vlock_regs[j]);
j++;
}
}
}
pr_info("%s done\n", __func__);
}
static void vlock_enable_step3(void)
{
unsigned int m_reg_value, tmp_value, abs_val;
unsigned int hiu_reg_addr;
unsigned int hiu_reg_addr, i;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL)
hiu_reg_addr = HHI_HDMI_PLL_CNTL1;
else
hiu_reg_addr = HHI_HDMI_PLL_CNTL2;
/*vs_i*/
tmp_value = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
abs_val = abs(vlock_log_last_ivcnt - tmp_value);
if ((abs_val > vlock_log_delta_ivcnt) &&
(vlock_log_delta_en & (1 << 0)))
pr_info("%s: abs_ivcnt over 0x%x:0x%x(last:0x%x,cur:0x%x)\n",
__func__, vlock_log_delta_ivcnt,
abs_val, vlock_log_last_ivcnt, tmp_value);
vlock_log_last_ivcnt = tmp_value;
/*vs_o*/
tmp_value = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
abs_val = abs(vlock_log_last_ovcnt - tmp_value);
if ((abs_val > vlock_log_delta_ovcnt) &&
(vlock_log_delta_en & (1 << 1)))
pr_info("%s: abs_ovcnt over 0x%x:0x%x(last:0x%x,cur:0x%x)\n",
__func__, vlock_log_delta_ovcnt,
abs_val, vlock_log_last_ivcnt, tmp_value);
vlock_log_last_ovcnt = tmp_value;
/*delta_vs*/
abs_val = abs(vlock_log_last_ovcnt - vlock_log_last_ivcnt);
if ((abs_val > vlock_log_delta_vcnt) && (vlock_log_delta_en & (1 << 2)))
pr_info("%s: abs_vcnt over 0x%x:0x%x(ivcnt:0x%x,ovcnt:0x%x)\n",
__func__, vlock_log_delta_vcnt,
abs_val, vlock_log_last_ivcnt, vlock_log_last_ovcnt);
m_reg_value = READ_VPP_REG(VPU_VLOCK_RO_M_INT_FRAC);
if (vlock_log_en && (vlock_log_cnt < vlock_log_size)) {
vlock_log[vlock_log_cnt].pll_frac = (m_reg_value & 0xfff) >> 2;
vlock_log[vlock_log_cnt].pll_m = (m_reg_value >> 16) & 0x1ff;
for (i = 0; i < VLOCK_REG_NUM; i++)
vlock_log[vlock_log_cnt].vlock_regs[i] =
READ_VPP_REG(0x3000 + i);
vlock_log_cnt++;
}
if (m_reg_value == 0) {
vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET;
if (vlock_debug & 0x100)
@@ -4783,18 +4969,33 @@ static void vlock_enable_step3(void)
__func__);
return;
}
/*vlsi suggest config:don't enable load signal,*/
/*on gxtvbb this load signal will effect SSG,*/
/*which may result in flashes black*/
amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL6, &tmp_value);
if (is_meson_gxtvbb_cpu() && (((tmp_value >> 21) & 0x3) != 2))
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6, 2, 21, 2);
/*frac*/
amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value);
abs_val = abs(((m_reg_value & 0xfff) >> 2) - (tmp_value & 0xfff));
if ((abs_val < vlock_delta_limit_frac) && (abs_val > 2)) {
if ((abs_val > vlock_log_delta_frac) &&
(vlock_log_delta_en & (1 << 3)))
pr_info("vlock frac delta:%d(0x%x,0x%x)\n",
abs_val, ((m_reg_value & 0xfff) >> 2),
(tmp_value & 0xfff));
if (abs_val > vlock_delta_limit) {
tmp_value = (tmp_value & 0xfffff000) |
((m_reg_value & 0xfff) >> 2);
amvecm_hiu_reg_write(hiu_reg_addr, tmp_value);
}
/*M*/
/*m*/
amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &tmp_value);
abs_val = abs(((m_reg_value >> 16) & 0x1ff) - (tmp_value & 0x1ff));
if (abs_val <= vlock_delta_limit_m) {
if ((abs_val > vlock_log_delta_m) && (vlock_log_delta_en & (1 << 4)))
pr_info("vlock m delta:%d(0x%x,0x%x)\n",
abs_val, ((m_reg_value >> 16) & 0x1ff),
(tmp_value & 0x1ff));
if (((m_reg_value >> 16) & 0x1ff) != (tmp_value & 0x1ff)) {
tmp_value = (tmp_value & 0xfffffe00) |
((m_reg_value >> 16) & 0x1ff);
amvecm_hiu_reg_write(HHI_HDMI_PLL_CNTL, tmp_value);
@@ -4818,6 +5019,7 @@ void amve_vlock_process(struct vframe_s *vf)
vinfo = get_current_vinfo();
input_hz = vlock_check_input_hz(vf);
output_hz = vlock_check_output_hz(vinfo->sync_duration_num);
vlock_dis_cnt_no_vf = 0;
if (vecm_latch_flag & FLAG_VLOCK_EN) {
vlock_enable_step1(vf, vinfo, input_hz, output_hz);
vlock_en = 1;
@@ -4829,23 +5031,18 @@ void amve_vlock_process(struct vframe_s *vf)
}
if (vlock_en == 1) {
if (((input_hz != output_hz) && (vlock_adapt == 0)) ||
(input_hz == 0) || (output_hz == 0)) {
vlock_dis_cnt_step1++;
(input_hz == 0) || (output_hz == 0) ||
(((vf->type_original & VIDTYPE_TYPEMASK)
!= VIDTYPE_PROGRESSIVE) &&
is_meson_txlx_package_962E())) {
if ((vlock_state != VLOCK_STATE_DISABLE_STEP2_DONE) &&
(vlock_dis_cnt_step1 >
vlock_dis_cnt_step1_limit) &&
(vlock_state != VLOCK_STATE_NULL)) {
(vlock_state != VLOCK_STATE_NULL))
vlock_disable_step1();
if (vlock_debug & 0x1)
pr_info("[%s]auto disable vlock module for no support case!!!\n",
__func__);
} else
vlock_state = VLOCK_STATE_DISABLE_STEP1;
if (vlock_debug & 0x1)
pr_info("[%s]auto disable vlock module for no support case!!!\n",
__func__);
return;
}
vlock_dis_cnt_step1 = 0;
if (vlock_state == VLOCK_STATE_ENABLE_STEP1)
vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET;
vlock_vmode_check();
if ((vinfo->mode != pre_vmode) ||
(vf->source_type != pre_source_type) ||
@@ -4853,16 +5050,13 @@ void amve_vlock_process(struct vframe_s *vf)
(input_hz != pre_input_freq) ||
(output_hz != pre_output_freq) ||
vlock_vmode_changed ||
(vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET) ||
(vlock_state == VLOCK_STATE_ENABLE_STEP1)) {
if (vlock_sync_limit_flag++ > vlock_en_cnt_step1_limit)
vlock_enable_step1(vf, vinfo,
input_hz, output_hz);
else
vlock_state = VLOCK_STATE_ENABLE_STEP1;
return;
}
if (vlock_state == VLOCK_STATE_ENABLE_STEP1_DONE) {
(vlock_state == VLOCK_STATE_ENABLE_FORCE_RESET))
vlock_enable_step1(vf, vinfo, input_hz, output_hz);
if ((vlock_sync_limit_flag < 10) &&
(vlock_state >= VLOCK_STATE_ENABLE_STEP1_DONE))
vlock_sync_limit_flag++;
if ((vlock_sync_limit_flag == 5) &&
(vlock_state == VLOCK_STATE_ENABLE_STEP1_DONE)) {
/*input_vs_cnt =*/
/*READ_VPP_REG_BITS(VPU_VLOCK_RO_VS_I_DIST,*/
/* 0, 28);*/
@@ -4876,20 +5070,18 @@ void amve_vlock_process(struct vframe_s *vf)
/*cal accum0 value*/
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);
vlock_state = VLOCK_STATE_ENABLE_STEP2_DONE;
return;
} else if (vlock_dynamic_adjust &&
(vlock_sync_limit_flag > 5) &&
(vlock_state == VLOCK_STATE_ENABLE_STEP2_DONE) &&
(is_meson_gxtvbb_cpu() || is_meson_txl_cpu()) &&
(cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) &&
(vlock_mode == VLOCK_MODE_MANUAL_PLL)) {
vlock_enable_step3();
return;
}
}
}
void amve_vlock_resume(void)
{
vlock_sync_limit_flag = 0;
if ((vlock_en == 0) || (vlock_state ==
VLOCK_STATE_DISABLE_STEP2_DONE) ||
(vlock_state == VLOCK_STATE_NULL))
@@ -4898,11 +5090,11 @@ void amve_vlock_resume(void)
vlock_disable_step2();
return;
}
vlock_dis_cnt_step1++;
vlock_dis_cnt_no_vf++;
if ((vlock_state != VLOCK_STATE_DISABLE_STEP2_DONE) &&
(vlock_dis_cnt_step1 > vlock_dis_cnt_step1_limit)) {
(vlock_dis_cnt_no_vf > vlock_dis_cnt_no_vf_limit)) {
vlock_disable_step1();
vlock_dis_cnt_step1 = 0;
vlock_dis_cnt_no_vf = 0;
if (vlock_debug & 0x1)
pr_info("[%s]auto disable vlock module for no vframe & run disable step1.!!!\n",
__func__);
@@ -4910,6 +5102,12 @@ void amve_vlock_resume(void)
if (vlock_debug & 0x1)
pr_info("[%s]auto disable vlock module for no vframe!!!\n",
__func__);
if (vlock_dynamic_adjust &&
(vlock_sync_limit_flag > 5) &&
(vlock_state == VLOCK_STATE_ENABLE_STEP2_DONE) &&
(cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) &&
(vlock_mode == VLOCK_MODE_MANUAL_PLL))
vlock_enable_step3();
}
void vlock_param_set(unsigned int val, enum vlock_param_e sel)
@@ -4927,11 +5125,8 @@ void vlock_param_set(unsigned int val, enum vlock_param_e sel)
case VLOCK_DIS_CNT_LIMIT:
vlock_dis_cnt_limit = val;
break;
case VLOCK_DELTA_LIMIT_FRAC:
vlock_delta_limit_frac = val;
break;
case VLOCK_DELTA_LIMIT_M:
vlock_delta_limit_m = val;
case VLOCK_DELTA_LIMIT:
vlock_delta_limit = val;
break;
case VLOCK_DEBUG:
vlock_debug = val;
@@ -4939,11 +5134,8 @@ void vlock_param_set(unsigned int val, enum vlock_param_e sel)
case VLOCK_DYNAMIC_ADJUST:
vlock_dynamic_adjust = val;
break;
case VLOCK_DIS_CNT_STEP1_LIMIT:
vlock_dis_cnt_step1_limit = val;
break;
case VLOCK_EN_CNT_STEP1_LIMIT:
vlock_en_cnt_step1_limit = val;
case VLOCK_DIS_CNT_NO_VF_LIMIT:
vlock_dis_cnt_no_vf_limit = val;
break;
default:
pr_info("%s:unknown vlock param:%d\n", __func__, sel);
@@ -4958,8 +5150,7 @@ void vlock_status(void)
pr_info("vlock_en:%d\n", vlock_en);
pr_info("vlock_adapt:%d\n", vlock_adapt);
pr_info("vlock_dis_cnt_limit:%d\n", vlock_dis_cnt_limit);
pr_info("vlock_delta_limit_frac:%d\n", vlock_delta_limit_frac);
pr_info("vlock_delta_limit_m:%d\n", vlock_delta_limit_m);
pr_info("vlock_delta_limit:%d\n", vlock_delta_limit);
pr_info("vlock_debug:0x%x\n", vlock_debug);
pr_info("vlock_dynamic_adjust:%d\n", vlock_dynamic_adjust);
pr_info("vlock_state:%d\n", vlock_state);
@@ -4969,9 +5160,8 @@ void vlock_status(void)
pr_info("pre_hiu_reg_frac:0x%x\n", pre_hiu_reg_frac);
pr_info("vlock_dis_cnt:%d\n", vlock_dis_cnt);
pr_info("pre_vout_mode:%s\n", pre_vout_mode);
pr_info("vlock_dis_cnt_step1:%d\n", vlock_dis_cnt_step1);
pr_info("vlock_dis_cnt_step1_limit:%d\n", vlock_dis_cnt_step1_limit);
pr_info("vlock_en_cnt_step1_limit:%d\n", vlock_en_cnt_step1_limit);
pr_info("vlock_dis_cnt_no_vf:%d\n", vlock_dis_cnt_no_vf);
pr_info("vlock_dis_cnt_no_vf_limit:%d\n", vlock_dis_cnt_no_vf_limit);
}
void vlock_reg_dump(void)
{
@@ -4988,6 +5178,7 @@ void vlock_reg_dump(void)
/* sharpness process begin */
void sharpness_process(struct vframe_s *vf)
{
return;
}
/* sharpness process end */

38
drivers/amlogic/media/enhancement/amvecm/amve.h
View File

@@ -61,14 +61,12 @@ enum vlock_param_e {
VLOCK_ADAPT,
VLOCK_MODE,
VLOCK_DIS_CNT_LIMIT,
VLOCK_DELTA_LIMIT_FRAC,
VLOCK_DELTA_LIMIT_M,
VLOCK_DELTA_LIMIT,
VLOCK_DEBUG,
VLOCK_DYNAMIC_ADJUST,
VLOCK_STATE,
VLOCK_SYNC_LIMIT_FLAG,
VLOCK_DIS_CNT_STEP1_LIMIT,
VLOCK_EN_CNT_STEP1_LIMIT,
VLOCK_DIS_CNT_NO_VF_LIMIT,
VLOCK_PARAM_MAX,
};
@@ -84,6 +82,20 @@ extern struct tcon_gamma_table_s video_gamma_table_g_adj;
extern struct tcon_gamma_table_s video_gamma_table_b_adj;
extern struct tcon_rgb_ogo_s video_rgb_ogo;
extern int glb_scurve[65];
extern int glb_clash_curve[65];
extern int glb_pst_gamma[65];
extern int gma_scurve0[65];
extern int gma_scurve1[65];
extern int gma_scurvet[65];
extern int clash_curve[65];
extern int clsh_scvbld[65];
extern int blk_gma_crv[65];
extern int blk_gma_bld[65];
extern int blkwht_ebld[65];
extern spinlock_t vpp_lcd_gamma_lock;
void ve_on_vs(struct vframe_s *vf);
@@ -105,7 +117,7 @@ extern void ve_disable_dnlp(void);
extern void vpp_enable_lcd_gamma_table(void);
extern void vpp_disable_lcd_gamma_table(void);
extern void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask);
extern void init_write_gamma_table(u16 *data, u32 rgb_mask);
extern void amve_write_gamma_table(u16 *data, u32 rgb_mask);
extern void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p);
extern void vpp_phase_lock_on_vs(unsigned int cycle,
unsigned int stamp,
@@ -134,6 +146,9 @@ extern void amve_vlock_resume(void);
extern void vlock_param_set(unsigned int val, enum vlock_param_e sel);
extern void vlock_status(void);
extern void vlock_reg_dump(void);
extern void vlock_log_start(void);
extern void vlock_log_stop(void);
extern void vlock_log_print(void);
int amvecm_hiu_reg_read(unsigned int reg, unsigned int *val);
int amvecm_hiu_reg_write(unsigned int reg, unsigned int val);
@@ -161,6 +176,7 @@ extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
/* #if defined(CONFIG_ARCH_MESON2) */
/* unsigned long long ve_get_vs_cnt(void); */
/* #endif */
extern int video_rgb_ogo_xvy_mtx;
#define VLOCK_STATE_NULL 0
#define VLOCK_STATE_ENABLE_STEP1_DONE 1
@@ -168,8 +184,16 @@ extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#define VLOCK_STATE_DISABLE_STEP1_DONE 3
#define VLOCK_STATE_DISABLE_STEP2_DONE 4
#define VLOCK_STATE_ENABLE_FORCE_RESET 5
#define VLOCK_STATE_ENABLE_STEP1 6
#define VLOCK_STATE_DISABLE_STEP1 7
/* video lock */
#define VLOCK_MODE_ENC 0
#define VLOCK_MODE_AUTO_PLL 1
#define VLOCK_MODE_MANUAL_PLL 2
#define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/
/* 0:enc;1:pll;2:manual pll */
extern unsigned int vlock_mode;
extern unsigned int vlock_en;
#endif

1436
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

File diff suppressed because it is too large Load Diff

8
drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h
View File

@@ -57,16 +57,16 @@ static struct am_regs_s vlock_pll_in50hz_out60hz = {
{REG_TYPE_VCBUS, 0x3000, 0xffffffff, 0x07f13f1b },
{REG_TYPE_VCBUS, 0x3001, 0xffffffff, 0x04053c32 },
{REG_TYPE_VCBUS, 0x3002, 0xffffffff, 0x06000000 },
{REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x2055c55c },
{REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x0065c65c },
{REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x20680680 },
{REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x00000000 },
{REG_TYPE_VCBUS, 0x3005, 0xffffffff, 0x00080000 },
{REG_TYPE_VCBUS, 0x3006, 0xffffffff, 0x00070000 },
{REG_TYPE_VCBUS, 0x3007, 0xffffffff, 0x00000000 },
{REG_TYPE_VCBUS, 0x3008, 0xffffffff, 0x00000000 },
{REG_TYPE_VCBUS, 0x3009, 0xffffffff, 0x00100000 },
{REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x00100000 },
{REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x00004000 },
{REG_TYPE_VCBUS, 0x300b, 0xffffffff, 0x00100000 },
{REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0x00010000 },
{REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0x00000000 },
{REG_TYPE_VCBUS, 0x300d, 0xffffffff, 0x00004000 },
{REG_TYPE_VCBUS, 0x3010, 0xffffffff, 0x20001000 },
{REG_TYPE_VCBUS, 0x3016, 0xffffffff, 0x0003de00 },

183
drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h
View File

@@ -149,6 +149,7 @@
#define VPP_VE_DEMO_CENTER_BAR 0x1da3
#define VPP_VE_H_V_SIZE 0x1da4
#define VPP_PSR_H_V_SIZE 0x1da5
#define VPP_OUT_H_V_SIZE 0x1da5
#define VPP_VDO_MEAS_CTRL 0x1da8
#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9
#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa
@@ -203,6 +204,14 @@
#define VPP_VD2_CLIP_MISC0 0x1de3
#define VPP_VD2_CLIP_MISC1 0x1de4
/*txlx new add*/
#define VPP_DAT_CONV_PARA0 0x1d94
#define VPP_DAT_CONV_PARA1 0x1d95
#define VD1_IF0_GEN_REG3 0x1aa7
#define VD2_IF0_GEN_REG3 0x1aa8
#define VPP2_DUMMY_DATA 0x1900
#define VPP2_LINE_IN_LENGTH 0x1901
#define VPP2_PIC_IN_HEIGHT 0x1902
@@ -442,16 +451,15 @@
#define VIU_EOTF_COEF11_12 0x31d3
#define VIU_EOTF_COEF20_21 0x31d4
#define VIU_EOTF_COEF22_RS 0x31d5
#define VIU_EOTF_LUT_ADDR_PORT 0x31d6
#define VIU_EOTF_LUT_DATA_PORT 0x31d7
#define VIU_EOTF_LUT_ADDR_PORT 0x31d6
#define VIU_EOTF_LUT_DATA_PORT 0x31d7
#define VIU_EOTF_3X3_OFST_0 0x31d8
#define VIU_EOTF_3X3_OFST_1 0x31d9
/* sharpness */
#define SRSHARP0_PK_FINALGAIN_HP_BP 0x3222
#define SRSHARP0_SHARP_PK_NR_ENABLE 0x3227
#define SRSHARP0_PK_NR_ENABLE 0x3227
#define SRSHARP0_SHARP_DNLP_EN 0x3245
#define SRSHARP1_PK_FINALGAIN_HP_BP 0x32a2
#define SRSHARP1_SHARP_PK_NR_ENABLE 0x32a7
#define SRSHARP1_SHARP_DNLP_EN 0x32c5
/*sr0 sr1 ybic cbic*/
#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 0x3258
@@ -459,30 +467,167 @@
#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 0x325c
#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 0x325e
#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 0x32d8
#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da
#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 0x32dc
#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de
/*sr0 sr1 lti cti*/
#define SRSHARP0_HCTI_FLT_CLP_DC 0x322e/*bit28*/
#define SRSHARP0_HLTI_FLT_CLP_DC 0x3234
#define SRSHARP0_VLTI_FLT_CON_CLP 0x323a/*bit14*/
#define SRSHARP0_VCTI_FLT_CON_CLP 0x323f
#define SRSHARP1_HCTI_FLT_CLP_DC 0x32ae/*bit28*/
#define SRSHARP1_HLTI_FLT_CLP_DC 0x32b4
#define SRSHARP1_VLTI_FLT_CON_CLP 0x32ba/*bit14*/
#define SRSHARP1_VCTI_FLT_CON_CLP 0x32bf
/*sr0 sr1 dejaggy/direction/dering*/
#define SRSHARP0_DEJ_CTRL 0x3264/*bit 0*/
#define SRSHARP0_SR3_DRTLPF_EN 0x3266/*bit 0-2*/
#define SRSHARP0_SR3_DERING_CTRL 0x326b/*bit 28-30*/
#define SRSHARP1_DEJ_CTRL 0x32e4/*bit 0*/
#define SRSHARP1_SR3_DRTLPF_EN 0x32e6/*bit 0-2*/
#define SRSHARP1_SR3_DERING_CTRL 0x32eb/*bit 28-30*/
/*sr4 add*/
#define SRSHARP0_SR3_DRTLPF_THETA 0x3273
#define SRSHARP0_SATPRT_CTRL 0x3274
#define SRSHARP0_SATPRT_DIVM 0x3275
#define SRSHARP0_SATPRT_LMT_RGB 0x3276
#define SRSHARP0_DB_FLT_CTRL 0x3277
#define SRSHARP0_DB_FLT_YC_THRD 0x3278
#define SRSHARP0_DB_FLT_RANDLUT 0x3279
#define SRSHARP0_DB_FLT_PXI_THRD 0x327a
#define SRSHARP0_DB_FLT_SEED_Y 0x327b
#define SRSHARP0_DB_FLT_SEED_U 0x327c
#define SRSHARP0_DB_FLT_SEED_V 0x327d
#define SRSHARP0_PKGAIN_VSLUMA_LUT_L 0x327e
#define SRSHARP0_PKGAIN_VSLUMA_LUT_H 0x327f
#define SRSHARP0_PKOSHT_VSLUMA_LUT_L 0x3203
#define SRSHARP0_PKOSHT_VSLUMA_LUT_H 0x3204
/*sharpness reg*/
#define SRSHARP1_SHARP_HVSIZE 0x3280
#define SRSHARP1_SHARP_HVBLANK_NUM 0x3281
#define SRSHARP1_NR_GAUSSIAN_MODE 0x3282
#define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE 0x3285
#define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT 0x3286
#define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE 0x3287
#define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT 0x3288
#define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE 0x3289
#define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT 0x328a
#define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE 0x328b
#define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT 0x328c
#define SRSHARP1_PK_CIRFB_LPF_MODE 0x328d
#define SRSHARP1_PK_DRTFB_LPF_MODE 0x328e
#define SRSHARP1_PK_CIRFB_HP_CORING 0x328f
#define SRSHARP1_PK_CIRFB_BP_CORING 0x3290
#define SRSHARP1_PK_DRTFB_HP_CORING 0x3291
#define SRSHARP1_PK_DRTFB_BP_CORING 0x3292
#define SRSHARP1_PK_CIRFB_BLEND_GAIN 0x3293
#define SRSHARP1_NR_ALPY_SSD_GAIN_OFST 0x3294
#define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE 0x3295
#define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT 0x3296
#define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE 0x3297
#define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT 0x3298
#define SRSHARP1_NR_ALP0_MIN_MAX 0x3299
#define SRSHARP1_NR_ALP1_MIERR_CORING 0x329a
#define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE 0x329b
#define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT 0x329c
#define SRSHARP1_NR_ALP1_MIN_MAX 0x329d
#define SRSHARP1_PK_ALP2_MIERR_CORING 0x329e
#define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE 0x329f
#define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT 0x32a0
#define SRSHARP1_PK_ALP2_MIN_MAX 0x32a1
#define SRSHARP1_PK_FINALGAIN_HP_BP 0x32a2
#define SRSHARP1_PK_OS_HORZ_CORE_GAIN 0x32a3
#define SRSHARP1_PK_OS_VERT_CORE_GAIN 0x32a4
#define SRSHARP1_PK_OS_ADPT_MISC 0x32a5
#define SRSHARP1_PK_OS_STATIC 0x32a6
#define SRSHARP1_PK_NR_ENABLE 0x32a7
#define SRSHARP1_PK_DRT_SAD_MISC 0x32a8
#define SRSHARP1_NR_TI_DNLP_BLEND 0x32a9
#define SRSHARP1_TI_DIR_CORE_ALPHA 0x32aa
#define SRSHARP1_CTI_DIR_ALPHA 0x32ab
#define SRSHARP1_LTI_CTI_DF_GAIN 0x32ac
#define SRSHARP1_LTI_CTI_DIR_AC_DBG 0x32ad
#define SRSHARP1_HCTI_FLT_CLP_DC 0x32ae
#define SRSHARP1_HCTI_BST_GAIN 0x32af
#define SRSHARP1_HCTI_BST_CORE 0x32b0
#define SRSHARP1_HCTI_CON_2_GAIN_0 0x32b1
#define SRSHARP1_HCTI_CON_2_GAIN_1 0x32b2
#define SRSHARP1_HCTI_OS_MARGIN 0x32b3
#define SRSHARP1_HLTI_FLT_CLP_DC 0x32b4
#define SRSHARP1_HLTI_BST_GAIN 0x32b5
#define SRSHARP1_HLTI_BST_CORE 0x32b6
#define SRSHARP1_HLTI_CON_2_GAIN_0 0x32b7
#define SRSHARP1_HLTI_CON_2_GAIN_1 0x32b8
#define SRSHARP1_HLTI_OS_MARGIN 0x32b9
#define SRSHARP1_VLTI_FLT_CON_CLP 0x32ba
#define SRSHARP1_VLTI_BST_GAIN 0x32bb
#define SRSHARP1_VLTI_BST_CORE 0x32bc
#define SRSHARP1_VLTI_CON_2_GAIN_0 0x32bd
#define SRSHARP1_VLTI_CON_2_GAIN_1 0x32be
#define SRSHARP1_VCTI_FLT_CON_CLP 0x32bf
#define SRSHARP1_VCTI_BST_GAIN 0x32c0
#define SRSHARP1_VCTI_BST_CORE 0x32c1
#define SRSHARP1_VCTI_CON_2_GAIN_0 0x32c2
#define SRSHARP1_VCTI_CON_2_GAIN_1 0x32c3
#define SRSHARP1_SHARP_3DLIMIT 0x32c4
#define SRSHARP1_DNLP_EN 0x32c5
#define SRSHARP1_DNLP_00 0x32c6
#define SRSHARP1_DNLP_01 0x32c7
#define SRSHARP1_DNLP_02 0x32c8
#define SRSHARP1_DNLP_03 0x32c9
#define SRSHARP1_DNLP_04 0x32ca
#define SRSHARP1_DNLP_05 0x32cb
#define SRSHARP1_DNLP_06 0x32cc
#define SRSHARP1_DNLP_07 0x32cd
#define SRSHARP1_DNLP_08 0x32ce
#define SRSHARP1_DNLP_09 0x32cf
#define SRSHARP1_DNLP_10 0x32d0
#define SRSHARP1_DNLP_11 0x32d1
#define SRSHARP1_DNLP_12 0x32d2
#define SRSHARP1_DNLP_13 0x32d3
#define SRSHARP1_DNLP_14 0x32d4
#define SRSHARP1_DNLP_15 0x32d5
#define SRSHARP1_DEMO_CRTL 0x32d6
#define SRSHARP1_SHARP_SR2_CTRL 0x32d7
#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 0x32d8
#define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 0x32d9
#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da
#define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 0x32db
#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 0x32dc
#define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 0x32dd
#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de
#define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 0x32df
#define SRSHARP1_SHARP_SR2_MISC 0x32e0
#define SRSHARP1_SR3_SAD_CTRL 0x32e1
#define SRSHARP1_SR3_PK_CTRL0 0x32e2
#define SRSHARP1_SR3_PK_CTRL1 0x32e3
#define SRSHARP1_DEJ_CTRL 0x32e4
#define SRSHARP1_DEJ_ALPHA 0x32e5
#define SRSHARP1_SR3_DRTLPF_EN 0x32e6
#define SRSHARP1_SR3_DRTLPF_ALPHA_0 0x32e7
#define SRSHARP1_SR3_DRTLPF_ALPHA_1 0x32e8
#define SRSHARP1_SR3_DRTLPF_ALPHA_2 0x32e9
#define SRSHARP1_SR3_DRTLPF_ALPHA_OFST 0x32ea
#define SRSHARP1_SR3_DERING_CTRL 0x32eb
#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 0x32ec
#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 0x32ed
#define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 0x32ee
#define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 0x32ef
#define SRSHARP1_SR3_DERING_GAINVS_MADSAD 0x32f0
#define SRSHARP1_SR3_DERING_GAINVS_VR2MAX 0x32f1
#define SRSHARP1_SR3_DERING_PARAM0 0x32f2
#define SRSHARP1_SR3_DRTLPF_THETA 0x32f3
#define SRSHARP1_SATPRT_CTRL 0x32f4
#define SRSHARP1_SATPRT_DIVM 0x32f5
#define SRSHARP1_SATPRT_LMT_RGB 0x32f6
#define SRSHARP1_DB_FLT_CTRL 0x32f7
#define SRSHARP1_DB_FLT_YC_THRD 0x32f8
#define SRSHARP1_DB_FLT_RANDLUT 0x32f9
#define SRSHARP1_DB_FLT_PXI_THRD 0x32fa
#define SRSHARP1_DB_FLT_SEED_Y 0x32fb
#define SRSHARP1_DB_FLT_SEED_U 0x32fc
#define SRSHARP1_DB_FLT_SEED_V 0x32fd
#define SRSHARP1_PKGAIN_VSLUMA_LUT_L 0x32fe
#define SRSHARP1_PKGAIN_VSLUMA_LUT_H 0x32ff
#define SRSHARP1_PKOSHT_VSLUMA_LUT_L 0x3283
#define SRSHARP1_PKOSHT_VSLUMA_LUT_H 0x3284
/*ve dither*/
#define VPP_VE_DITHER_CTRL 0x3120
/* for pll bug */
#define HHI_HDMI_PLL_CNTL 0x10c8

8
drivers/amlogic/media/video_sink/video.c
View File

@@ -4603,7 +4603,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
amlog_mask_if(toggle_cnt > 0, LOG_MASK_FRAMESKIP,
"skipped\n");
#if DEBUG_TMP
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
refresh_on_vs(vf);
@@ -4613,7 +4613,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
vf, CSC_FLAG_CHECK_OUTPUT) == 1)
break;
#endif
#if DEBUG_TMP
if (is_dolby_vision_enable()
&& dolby_vision_need_wait())
break;
@@ -4724,6 +4724,7 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
if (is_dolby_vision_enable()
&& dolby_vision_need_wait())
break;
#endif
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
refresh_on_vs(vf);
if (amvecm_on_vs(
@@ -4731,7 +4732,6 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
? cur_dispbuf : NULL,
vf, CSC_FLAG_CHECK_OUTPUT) == 1)
break;
#endif
#endif
vf = video_vf_get();
if (!vf)
@@ -4810,13 +4810,11 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
#endif
SET_FILTER:
#if DEBUG_TMP
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
amvecm_on_vs(
(cur_dispbuf != &vf_local) ? cur_dispbuf : NULL,
toggle_frame,
toggle_frame ? CSC_FLAG_TOGGLE_FRAME : 0);
#endif
#endif
/* filter setting management */
if ((frame_par_ready_to_set) || (frame_par_force_to_set)) {

32
include/linux/amlogic/media/amvecm/amvecm.h
View File

@@ -68,6 +68,28 @@
#define VPP_DEMO_CM_DIS (1 << 1)
#define VPP_DEMO_CM_EN (1 << 0)
/*PQ USER LATCH*/
#define PQ_USER_SR1_DERECTION_DIS (1 << 19)
#define PQ_USER_SR1_DERECTION_EN (1 << 18)
#define PQ_USER_SR0_DERECTION_DIS (1 << 17)
#define PQ_USER_SR0_DERECTION_EN (1 << 16)
#define PQ_USER_SR1_DEJAGGY_DIS (1 << 15)
#define PQ_USER_SR1_DEJAGGY_EN (1 << 14)
#define PQ_USER_SR0_DEJAGGY_DIS (1 << 13)
#define PQ_USER_SR0_DEJAGGY_EN (1 << 12)
#define PQ_USER_SR1_DERING_DIS (1 << 11)
#define PQ_USER_SR1_DERING_EN (1 << 10)
#define PQ_USER_SR0_DERING_DIS (1 << 9)
#define PQ_USER_SR0_DERING_EN (1 << 8)
#define PQ_USER_SR1_PK_DIS (1 << 7)
#define PQ_USER_SR1_PK_EN (1 << 6)
#define PQ_USER_SR0_PK_DIS (1 << 5)
#define PQ_USER_SR0_PK_EN (1 << 4)
#define PQ_USER_BLK_SLOPE (1 << 3)
#define PQ_USER_BLK_START (1 << 2)
#define PQ_USER_BLK_DIS (1 << 1)
#define PQ_USER_BLK_EN (1 << 0)
/*white balance latch*/
#define MTX_BYPASS_RGB_OGO (1 << 0)
#define MTX_RGB2YUVL_RGB_OGO (1 << 1)
@@ -160,9 +182,16 @@ static inline uint32_t READ_VPP_REG_BITS(uint32_t reg,
extern signed int vd1_brightness, vd1_contrast;
extern bool gamma_en;
extern void amvecm_on_vs(struct vframe_s *vf);
#define CSC_FLAG_TOGGLE_FRAME 1
#define CSC_FLAG_CHECK_OUTPUT 2
extern int amvecm_on_vs(
struct vframe_s *display_vf,
struct vframe_s *toggle_vf,
int flags);
extern void refresh_on_vs(struct vframe_s *vf);
extern void pc_mode_process(void);
extern void pq_user_latch_process(void);
/* master_display_info for display device */
struct hdr_metadata_info_s {
@@ -195,5 +224,6 @@ extern struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf);
extern void dolby_vision_dump_setting(int debug_flag);
extern void dolby_vision_dump_struct(void);
extern void enable_osd_path(int on);
extern void amvecm_wakeup_queue(void);
#endif /* AMVECM_H */

2
include/linux/amlogic/media/amvecm/ve.h
View File

@@ -317,6 +317,8 @@ struct hdr_osd_reg_s {
uint32_t viu_osd1_eotf_coef11_12; /* 0x1ad7 */
uint32_t viu_osd1_eotf_coef20_21; /* 0x1ad8 */
uint32_t viu_osd1_eotf_coef22_rs; /* 0x1ad9 */
uint32_t VIU_OSD1_EOTF_3X3_OFST_0; /* 0x1aa0*/
uint32_t VIU_OSD1_EOTF_3X3_OFST_1; /* 0x1aa1*/
uint32_t viu_osd1_oetf_ctl; /* 0x1adc */
struct hdr_osd_lut_s lut_val;
};