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drm/bridge: dw-hdmi-qp: Fix timer reference base error

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Set timer reference base According to the actual
refclk frequency, otherwise cec or ddc function
may be abnormal.

Change-Id: Id45af649182a5158a47ee2cadb1254f2dc855d52
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This commit is contained in:
Algea Cao
2024-02-19 21:02:38 +08:00
committed by Tao Huang
parent 9e65f43e46
commit 0a6460072f
3 changed files with 16 additions and 2 deletions
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8
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
View File

@@ -299,6 +299,8 @@ struct dw_hdmi_qp {
u32 flt_intr;
u32 earc_intr;
u32 refclk_rate;
struct mutex audio_mutex;
unsigned int sample_rate;
unsigned int audio_cts;
@@ -3782,9 +3784,11 @@ __dw_hdmi_probe(struct platform_device *pdev,
if (hdmi->plat_data->get_force_timing(hdmi->plat_data->phy_data))
hdmi->force_kernel_output = true;
hdmi->refclk_rate = hdmi->plat_data->get_refclk_rate(hdmi->plat_data->phy_data);
hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
hdmi_writel(hdmi, hdmi->refclk_rate, TIMER_BASE_CONFIG0);
hdmi->logo_plug_out = false;
if (hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data) == connector_status_connected &&
hdmi_readl(hdmi, I2CM_INTERFACE_CONTROL0)) {
@@ -4105,7 +4109,7 @@ void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
hdmi_writel(hdmi, hdmi->refclk_rate, TIMER_BASE_CONFIG0);
pinctrl_pm_select_default_state(dev);

9
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
View File

@@ -2906,6 +2906,13 @@ static struct drm_display_mode *dw_hdmi_rockchip_get_force_timing(void *data)
return &hdmi->force_mode;
}
static u32 dw_hdmi_rockchip_get_refclk_rate(void *data)
{
struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
return clk_get_rate(hdmi->hdmitx_ref);
}
static const struct drm_prop_enum_list color_depth_enum_list[] = {
{ 0, "Automatic" }, /* Prefer highest color depth */
{ 8, "24bit" },
@@ -3949,6 +3956,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
dw_hdmi_rockchip_set_hdcp14_mem;
plat_data->get_force_timing =
dw_hdmi_rockchip_get_force_timing;
plat_data->get_refclk_rate =
dw_hdmi_rockchip_get_refclk_rate;
plat_data->property_ops = &dw_hdmi_rockchip_property_ops;
secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id);

1
include/drm/bridge/dw_hdmi.h
View File

@@ -268,6 +268,7 @@ struct dw_hdmi_plat_data {
void (*set_ddc_io)(void *data, bool enable);
void (*set_hdcp14_mem)(void *data, bool enable);
struct drm_display_mode *(*get_force_timing)(void *data);
u32 (*get_refclk_rate)(void *data);
/* Vendor Property support */
const struct dw_hdmi_property_ops *property_ops;