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clk: rockchip: rk3568: Fix HCLK_ACDCDIG

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Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ifaf30bbdf88f24b330c0caa6861313070c5d2784
This commit is contained in:
Sugar Zhang
2020-10-18 11:39:01 +08:00
committed by Tao Huang
parent c66ee6a770
commit 0ac3329e47
2 changed files with 2 additions and 2 deletions
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2
drivers/clk/rockchip/clk-rk3568.c
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@@ -746,7 +746,7 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKGATE_CON(8), 2, GFLAGS,
&rk3568_audpwm_fracmux, RK3568_FRAC_MAX_PRATE),
GATE(HCLK_ACDCDIG_I2C, "hclk_acdcdig_i2c", "hclk_gic_audio", 0,
GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(8), 3, GFLAGS),
COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,

2
include/dt-bindings/clock/rk3568-cru.h
View File

@@ -157,7 +157,7 @@
#define SCLK_AUDPWM_SRC 97
#define SCLK_AUDPWM_FRAC 98
#define SCLK_AUDPWM 99
#define HCLK_ACDCDIG_I2C 100
#define HCLK_ACDCDIG 100
#define CLK_ACDCDIG_I2C 101
#define CLK_ACDCDIG_DAC 102
#define CLK_ACDCDIG_ADC 103