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Merge commit '5071891c1714b30b39bf79e4e0aa8ac953f4940c'
* commit '5071891c1714b30b39bf79e4e0aa8ac953f4940c': (258 commits)
arm64: dts: rockchip: rk3562-evb: fix uart_rts_gpios
drm/rockchip: vop3: update ygt2/4 triger condition for rk3528
ARM: dts: rockchip: rk3128-evb-ddr3-v10-linux: Fix sdmmc
ARM: dts: rockchip: rk3128: redefine sdmmc_pwren as GPIO function
drm/rockchip: dw-dp: Add support for drm_panel usage
ARM: dts: rockchip: rk312x: Update sdmmc node
video: rockchip: mpp: fix rkvdec2 link info err
soc: rockchip: opp_select: Fix restricting voltage error
arm64: dts: rockchip: rk3528: Set mclkin freq as 0 Hz default
arm64: dts: rockchip: rk3588: Set mclkin freq as 0 Hz default
arm64: dts: rockchip: rk3562: Set mclkin freq as 0 Hz default
drm/rockchip: vop3: add cluster frame reset
clk: rockchip: rk3528: Allow disable clk_400m_src
clk: rockchip: rk3128: fix up the sdmmc drv and sample set phase failed
drm/rockchip: vop2: adjust writeback commit time
media: rockchip: vicap fixes tasklet error for vb_done
media: rockchip: vicap: rk3562 add csirx data clk
arm64: dts: rockchip: rk3562: vicap add csirx data clk control
arm64: dts: rockchip: rk3528: Add SAIx_MCLK{OUT,IN} nodes
video: rockchip: mpp: change the way to refresh the dma cache
...
Change-Id: I50fef612c158b31c7def89895c13cc3757523be4
This commit is contained in:
Tao Huang
107
Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
Normal file
107
Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
Normal file
@@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip Clock Out Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Sugar Zhang <sugar.zhang@rock-chips.com>
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||||
|
||||
description: |
|
||||
This add support switch for clk-bidirection which located
|
||||
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
|
||||
and these config maybe located in many pieces of GRF,
|
||||
which hard to addressed in one single clk driver. so, we add
|
||||
this simple helper driver to address this situation.
|
||||
|
||||
In order to simplify implement and usage, and also for safety
|
||||
clk usage (avoid high freq glitch), we set all clk out as disabled
|
||||
(which means Input default for clk-bidrection) in the pre-stage,
|
||||
such boot-loader or init by HW default. And then set a safety freq
|
||||
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
|
||||
in drivers.
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|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,clk-out
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: parent clocks.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
rockchip,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Defines the bit shift of clk out enable.
|
||||
|
||||
rockchip,bit-set-to-disable:
|
||||
type: boolean
|
||||
description: |
|
||||
By default this clock sets the bit at bit-shift to enable the clock.
|
||||
Setting this property does the opposite: setting the bit disable
|
||||
the clock and clearing it enables the clock.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
- clock-output-names
|
||||
- rockchip,bit-shift
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Provider node:
|
||||
- |
|
||||
mclkin_sai0: mclkin-sai0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
clock-output-names = "mclk_sai0_from_io";
|
||||
};
|
||||
|
||||
mclkout_sai0: mclkout-sai0@ff040070 {
|
||||
compatible = "rockchip,clk-out";
|
||||
reg = <0 0xff040070 0 0x4>;
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||||
clocks = <&cru MCLK_SAI0_OUT2IO>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk_sai0_to_io";
|
||||
rockchip,bit-shift = <4>;
|
||||
};
|
||||
|
||||
# Clock mclkout Consumer node:
|
||||
- |
|
||||
ext_codec {
|
||||
clocks = <&mclkout_sai0>;
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||||
clock-names = "mclk";
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assigned-clocks = <&mclkout_sai0>;
|
||||
assigned-clock-rates = <12288000>;
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||||
pinctrl-names = "default";
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||||
pinctrl-0 = <&i2s0m0_mclk>;
|
||||
};
|
||||
|
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# Clock mclkin Consumer node:
|
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- |
|
||||
ext_codec {
|
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clocks = <&mclkin_sai0>;
|
||||
clock-names = "mclk";
|
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assigned-clocks = <&cru CLK_SAI0>;
|
||||
assigned-clock-parents = <&mclkin_sai0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_mclk>;
|
||||
};
|
||||
@@ -10,11 +10,6 @@ Required Properties:
|
||||
- compatible: CRU should be "rockchip,px30-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
|
||||
in clock-names
|
||||
- clock-names: Should contain the following:
|
||||
- "xin24m" for both PMUCRU and CRU
|
||||
- "gpll" for CRU (sourced from PMUCRU)
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
|
||||
@@ -10,6 +10,7 @@ Required properties:
|
||||
- "rockchip,rk3328-dfi" - for RK3328 SoCs.
|
||||
- "rockchip,rk3368-dfi" - for RK3368 SoCs.
|
||||
- "rockchip,rk3399-dfi" - for RK3399 SoCs.
|
||||
- "rockchip,rk3562-dfi" - for RK3562 SoCs.
|
||||
- "rockchip,rk3568-dfi" - for RK3568 SoCs.
|
||||
- "rockchip,rv1126-dfi" - for RV1126 SoCs.
|
||||
|
||||
|
||||
@@ -11,6 +11,7 @@ Required properties:
|
||||
- "rockchip,rk3328-dmc" - for RK3328 SoCs.
|
||||
- "rockchip,rk3368-dmc" - for RK3368 SoCs.
|
||||
- "rockchip,rk3399-dmc" - for RK3399 SoCs.
|
||||
- "rockchip,rk3562-dmc" - for RK3562 SoCs.
|
||||
- "rockchip,rk3568-dmc" - for RK3568 SoCs.
|
||||
- "rockchip,rk3588-dmc" - for RK3588 SoCs.
|
||||
- "rockchip,rv1126-dmc" - for RV1126 SoCs.
|
||||
|
||||
@@ -8,6 +8,9 @@ patternProperties:
|
||||
"connector-enable": if this connector should be enabled
|
||||
"connector-vp-id": which video port this connector attached to.
|
||||
The connector here should be hdmi0/1, dp0/1, mipi0/1
|
||||
"virtual-connector-count": the number of virtual connector devices.
|
||||
"virtualX-disconnected": Set specified virtual connector to disconnected.
|
||||
The X here should be less than virtual-connector-count.
|
||||
|
||||
Example:
|
||||
vconn {
|
||||
@@ -16,6 +19,8 @@ vconn {
|
||||
hdmi1-enable;
|
||||
hdmi0-vp-id = <0>;
|
||||
hdmi1-vp-id = <1>;
|
||||
virtual-connector-count = <2>;
|
||||
virtual1-disconnected;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -25,6 +25,7 @@ select:
|
||||
- rockchip,rk3368-gmac
|
||||
- rockchip,rk3399-gmac
|
||||
- rockchip,rk3528-gmac
|
||||
- rockchip,rk3562-gmac
|
||||
- rockchip,rk3568-gmac
|
||||
- rockchip,rk3588-gmac
|
||||
- rockchip,rv1106-gmac
|
||||
@@ -50,10 +51,12 @@ properties:
|
||||
- rockchip,rk3366-gmac
|
||||
- rockchip,rk3368-gmac
|
||||
- rockchip,rk3399-gmac
|
||||
- rockchip,rk3562-gmac
|
||||
- rockchip,rv1108-gmac
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3528-gmac
|
||||
- rockchip,rk3562-gmac
|
||||
- rockchip,rk3568-gmac
|
||||
- rockchip,rk3588-gmac
|
||||
- rockchip,rv1106-gmac
|
||||
|
||||
46
Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt
Normal file
46
Documentation/devicetree/bindings/rpmsg/rpmsg-rockchip.txt
Normal file
@@ -0,0 +1,46 @@
|
||||
* Rockchip RPMsg Platform Driver
|
||||
|
||||
The Rockchip RPMsg Platform Driver is used for Remote Processors Messaging.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
"rockchip,rk3568-rpmsg" for rk3568 SoCs.
|
||||
- mbox-names: mailbox name for "rpmsg-rx" or "rpmsg-tx".
|
||||
- mboxes: mailbox channel for rpmsg.
|
||||
- rockchip,vdev-nums: number of rpmsg instance.
|
||||
- rockchip,link-id: link_id of rpmsg instance. 4bit for master cpu_id and 4bit
|
||||
for remote cpu_id.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
Example:
|
||||
|
||||
rpmsg: rpmsg {
|
||||
compatible = "rockchip,rk3568-rpmsg";
|
||||
mbox-names = "rpmsg-rx", "rpmsg-tx";
|
||||
mboxes = <&mailbox 0 &mailbox 3>;
|
||||
rockchip,vdev-nums = <1>;
|
||||
rockchip,link-id = <0x03>;
|
||||
reg = <0x0 0x7c00000 0x0 0x20000>;
|
||||
memory-region = <&rpmsg_dma_reserved>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
rpmsg_reserved: rpmsg@7c00000 {
|
||||
reg = <0x0 0x7c00000 0x0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rpmsg_dma_reserved: rpmsg-dma@8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x8000000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
@@ -1008,6 +1008,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rv1126-evb-ddr3-v12-spi-nor.dtb \
|
||||
rv1126-evb-ddr3-v13.dtb \
|
||||
rk3036-evb.dtb \
|
||||
rk3036-evb1-ddr3-v10.dtb \
|
||||
rk3036-kylin.dtb \
|
||||
rk3066a-bqcurie2.dtb \
|
||||
rk3066a-marsboard.dtb \
|
||||
|
||||
@@ -645,6 +645,10 @@
|
||||
|
||||
&i2s {
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-0 = <&i2s_sclk
|
||||
&i2s_lrclktx
|
||||
&i2s_sdo
|
||||
&i2s_sdi>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
690
arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
Normal file
690
arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
Normal file
@@ -0,0 +1,690 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3036.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3036 EVB1 DDR3 V10 Board";
|
||||
compatible = "rockchip,rk3036-evb1-ddr3-v10", "rockchip,rk3036";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=uart8250,mmio32,0x20068000 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x20000000>;
|
||||
};
|
||||
|
||||
multi_sounds: multi-sounds {
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,name = "rockchip,rk3036-sounds";
|
||||
simple-audio-card,dai-link@0 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&i2s>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&acodec>;
|
||||
};
|
||||
};
|
||||
simple-audio-card,dai-link@1 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&i2s>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&hdmi>;
|
||||
};
|
||||
};
|
||||
simple-audio-card,dai-link@2 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&i2s>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&es8311>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spdiftx_codec: spdiftx-codec {
|
||||
status = "okay";
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
spdif_sound: spdif-sound {
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-sound";
|
||||
simple-audio-card,dai-link {
|
||||
mclk-fs = <256>;
|
||||
cpu {
|
||||
sound-dai = <&spdif_tx>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&spdiftx_codec>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: vdd-arm-regulator {
|
||||
compatible = "pwm-regulator";
|
||||
rockchip,pwm_id = <2>;
|
||||
pwms = <&pwm2 0 25000 0>;
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-init-microvolt = <1100000>;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_host: vcc-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_host";
|
||||
gpio = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&host_vbus_drv>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
xin32k: xin32k {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
|
||||
wifi_chip_type = "rk915";
|
||||
WIFI,poweren_gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
WIFI,host_wake_irq = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&acodec {
|
||||
spk_ctl_io = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
/delete-node/ opp-408000000;
|
||||
/delete-node/ opp-1200000000;
|
||||
};
|
||||
|
||||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
|
||||
phy = <&phy0>;
|
||||
phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
|
||||
phy-reset-duration = <10>; /* millisecond */
|
||||
|
||||
|
||||
/* If you're going to use Ethernet, you need an external clock
|
||||
* This is just a test(e.g: the accurate 50MHz what mac_ref need)
|
||||
* so cpu The frequency should be set to 600M
|
||||
*/
|
||||
assigned-clock-parents = <&cru PLL_APLL>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
rockchip,default-sample-phase = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
mali-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hevc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hevc_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "xin32k";
|
||||
};
|
||||
|
||||
es8311: es8311@18 {
|
||||
compatible = "everest,es8311";
|
||||
reg = <0x18>;
|
||||
clocks = <&cru SCLK_I2S_OUT>;
|
||||
clock-names = "mclk";
|
||||
adc-pga-gain = <8>;
|
||||
adc-volume = <0xdf>;
|
||||
dac-volume = <0xbf>;
|
||||
aec-mode = "adc left, adc right";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s_mclk>;
|
||||
|
||||
/*
|
||||
* in rk3036-evb-v10,es8311 is not actually connected
|
||||
* to PA,so we don't need spk-ctl-gpios
|
||||
*/
|
||||
/*spk-ctl-gpios = ;*/
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
rk628: rk628@50 {
|
||||
compatible = "rockchip,rk628";
|
||||
reg = <0x50>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
plugin-det-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
rk628,hdmi-in;
|
||||
rk628-dsi {
|
||||
//rockchip,dual-channel;
|
||||
dsi,eotp;
|
||||
dsi,video-mode;
|
||||
dsi,format = "rgb888";
|
||||
dsi,lanes = <4>;
|
||||
status = "okay";
|
||||
|
||||
rk628-panel {
|
||||
panel-init-sequence = [
|
||||
39 00 04 ff 98 81 03
|
||||
15 00 02 01 00
|
||||
15 00 02 02 00
|
||||
15 00 02 03 53
|
||||
15 00 02 04 53
|
||||
15 00 02 05 13
|
||||
15 00 02 06 04
|
||||
15 00 02 07 02
|
||||
15 00 02 08 02
|
||||
15 00 02 09 00
|
||||
15 00 02 0a 00
|
||||
15 00 02 0b 00
|
||||
15 00 02 0c 00
|
||||
15 00 02 0d 00
|
||||
15 00 02 0e 00
|
||||
15 00 02 0f 00
|
||||
15 00 02 10 00
|
||||
15 00 02 11 00
|
||||
15 00 02 12 00
|
||||
15 00 02 13 00
|
||||
15 00 02 14 00
|
||||
15 00 02 15 08
|
||||
15 00 02 16 10
|
||||
15 00 02 17 00
|
||||
15 00 02 18 08
|
||||
15 00 02 19 00
|
||||
15 00 02 1a 00
|
||||
15 00 02 1b 00
|
||||
15 00 02 1c 00
|
||||
15 00 02 1d 00
|
||||
15 00 02 1e c0
|
||||
15 00 02 1f 80
|
||||
15 00 02 20 02
|
||||
15 00 02 21 09
|
||||
15 00 02 22 00
|
||||
15 00 02 23 00
|
||||
15 00 02 24 00
|
||||
15 00 02 25 00
|
||||
15 00 02 26 00
|
||||
15 00 02 27 00
|
||||
15 00 02 28 55
|
||||
15 00 02 29 03
|
||||
15 00 02 2a 00
|
||||
15 00 02 2b 00
|
||||
15 00 02 2c 00
|
||||
15 00 02 2d 00
|
||||
15 00 02 2e 00
|
||||
15 00 02 2f 00
|
||||
15 00 02 30 00
|
||||
15 00 02 31 00
|
||||
15 00 02 32 00
|
||||
15 00 02 33 00
|
||||
15 00 02 34 04
|
||||
15 00 02 35 05
|
||||
15 00 02 36 05
|
||||
15 00 02 37 00
|
||||
15 00 02 38 3c
|
||||
15 00 02 39 35
|
||||
15 00 02 3a 00
|
||||
15 00 02 3b 40
|
||||
15 00 02 3c 00
|
||||
15 00 02 3d 00
|
||||
15 00 02 3e 00
|
||||
15 00 02 3f 00
|
||||
15 00 02 40 00
|
||||
15 00 02 41 88
|
||||
15 00 02 42 00
|
||||
15 00 02 43 00
|
||||
15 00 02 44 1f
|
||||
15 00 02 50 01
|
||||
15 00 02 51 23
|
||||
15 00 02 52 45
|
||||
15 00 02 53 67
|
||||
15 00 02 54 89
|
||||
15 00 02 55 ab
|
||||
15 00 02 56 01
|
||||
15 00 02 57 23
|
||||
15 00 02 58 45
|
||||
15 00 02 59 67
|
||||
15 00 02 5a 89
|
||||
15 00 02 5b ab
|
||||
15 00 02 5c cd
|
||||
15 00 02 5d ef
|
||||
15 00 02 5e 03
|
||||
15 00 02 5f 14
|
||||
15 00 02 60 15
|
||||
15 00 02 61 0c
|
||||
15 00 02 62 0d
|
||||
15 00 02 63 0e
|
||||
15 00 02 64 0f
|
||||
15 00 02 65 10
|
||||
15 00 02 66 11
|
||||
15 00 02 67 08
|
||||
15 00 02 68 02
|
||||
15 00 02 69 0a
|
||||
15 00 02 6a 02
|
||||
15 00 02 6b 02
|
||||
15 00 02 6c 02
|
||||
15 00 02 6d 02
|
||||
15 00 02 6e 02
|
||||
15 00 02 6f 02
|
||||
15 00 02 70 02
|
||||
15 00 02 71 02
|
||||
15 00 02 72 06
|
||||
15 00 02 73 02
|
||||
15 00 02 74 02
|
||||
15 00 02 75 14
|
||||
15 00 02 76 15
|
||||
15 00 02 77 0f
|
||||
15 00 02 78 0e
|
||||
15 00 02 79 0d
|
||||
15 00 02 7a 0c
|
||||
15 00 02 7b 11
|
||||
15 00 02 7c 10
|
||||
15 00 02 7d 06
|
||||
15 00 02 7e 02
|
||||
15 00 02 7f 0a
|
||||
15 00 02 80 02
|
||||
15 00 02 81 02
|
||||
15 00 02 82 02
|
||||
15 00 02 83 02
|
||||
15 00 02 84 02
|
||||
15 00 02 85 02
|
||||
15 00 02 86 02
|
||||
15 00 02 87 02
|
||||
15 00 02 88 08
|
||||
15 00 02 89 02
|
||||
15 00 02 8a 02
|
||||
39 00 04 ff 98 81 04
|
||||
15 00 02 00 80
|
||||
15 00 02 70 00
|
||||
15 00 02 71 00
|
||||
15 00 02 66 fe
|
||||
15 00 02 82 15
|
||||
15 00 02 84 15
|
||||
15 00 02 85 15
|
||||
15 00 02 3a 24
|
||||
15 00 02 32 ac
|
||||
15 00 02 8c 80
|
||||
15 00 02 3c f5
|
||||
15 00 02 88 33
|
||||
39 00 04 ff 98 81 01
|
||||
15 00 02 22 0a
|
||||
15 00 02 31 00
|
||||
15 00 02 53 78
|
||||
15 00 02 55 7b
|
||||
15 00 02 60 20
|
||||
15 00 02 61 00
|
||||
15 00 02 62 0d
|
||||
15 00 02 63 00
|
||||
15 00 02 a0 00
|
||||
15 00 02 a1 10
|
||||
15 00 02 a2 1c
|
||||
15 00 02 a3 13
|
||||
15 00 02 a4 15
|
||||
15 00 02 a5 26
|
||||
15 00 02 a6 1a
|
||||
15 00 02 a7 1d
|
||||
15 00 02 a8 67
|
||||
15 00 02 a9 1c
|
||||
15 00 02 aa 29
|
||||
15 00 02 ab 5b
|
||||
15 00 02 ac 26
|
||||
15 00 02 ad 28
|
||||
15 00 02 ae 5c
|
||||
15 00 02 af 30
|
||||
15 00 02 b0 31
|
||||
15 00 02 b1 32
|
||||
15 00 02 b2 00
|
||||
15 00 02 b1 2e
|
||||
15 00 02 b2 32
|
||||
15 00 02 b3 00
|
||||
15 00 02 c0 00
|
||||
15 00 02 c1 10
|
||||
15 00 02 c2 1c
|
||||
15 00 02 c3 13
|
||||
15 00 02 c4 15
|
||||
15 00 02 c5 26
|
||||
15 00 02 c6 1a
|
||||
15 00 02 c7 1d
|
||||
15 00 02 c8 67
|
||||
15 00 02 c9 1c
|
||||
15 00 02 ca 29
|
||||
15 00 02 cb 5b
|
||||
15 00 02 cc 26
|
||||
15 00 02 cd 28
|
||||
15 00 02 ce 5c
|
||||
15 00 02 cf 30
|
||||
15 00 02 d0 31
|
||||
15 00 02 d1 2e
|
||||
15 00 02 d2 32
|
||||
15 00 02 d3 00
|
||||
39 00 04 ff 98 81 00
|
||||
05 00 01 11
|
||||
05 01 01 29
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
|
||||
src-timing {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <720>;
|
||||
vactive = <1280>;
|
||||
hfront-porch = <48>;
|
||||
hsync-len = <8>;
|
||||
hback-porch = <52>;
|
||||
vfront-porch = <16>;
|
||||
vsync-len = <6>;
|
||||
vback-porch = <15>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
|
||||
dst-timing {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <720>;
|
||||
vactive = <1280>;
|
||||
hfront-porch = <48>;
|
||||
hsync-len = <8>;
|
||||
hback-porch = <52>;
|
||||
vfront-porch = <16>;
|
||||
vsync-len = <6>;
|
||||
vback-porch = <15>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-0 = <&i2s_sclk
|
||||
&i2s_lrclktx
|
||||
&i2s_sdo
|
||||
&i2s_sdi>;
|
||||
};
|
||||
|
||||
&mpp_srv {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif_tx {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
compatible = "rockchip,remotectl-pwm";
|
||||
remote_pwm_id = <3>;
|
||||
handle_cpu_id = <1>;
|
||||
remote_support_psci = <1>;
|
||||
|
||||
ir_key1 {
|
||||
rockchip,usercode = <0x4040>;
|
||||
rockchip,key_table =
|
||||
<0xf2 KEY_REPLY>,
|
||||
<0xba KEY_BACK>,
|
||||
<0xf4 KEY_UP>,
|
||||
<0xf1 KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xee KEY_RIGHT>,
|
||||
<0xbd KEY_HOME>,
|
||||
<0xea KEY_VOLUMEUP>,
|
||||
<0xe3 KEY_VOLUMEDOWN>,
|
||||
<0xe2 KEY_SEARCH>,
|
||||
<0xb2 KEY_POWER>,
|
||||
<0xbc KEY_MUTE>,
|
||||
<0xec KEY_MENU>,
|
||||
<0xbf 0x190>,
|
||||
<0xe0 0x191>,
|
||||
<0xe1 0x192>,
|
||||
<0xe9 183>,
|
||||
<0xe6 248>,
|
||||
<0xe8 185>,
|
||||
<0xe7 186>,
|
||||
<0xf0 388>,
|
||||
<0xbe 0x175>;
|
||||
};
|
||||
|
||||
ir_key2 {
|
||||
rockchip,usercode = <0xff00>;
|
||||
rockchip,key_table =
|
||||
<0xf9 KEY_HOME>,
|
||||
<0xbf KEY_BACK>,
|
||||
<0xfb KEY_MENU>,
|
||||
<0xaa KEY_REPLY>,
|
||||
<0xb9 KEY_UP>,
|
||||
<0xe9 KEY_DOWN>,
|
||||
<0xb8 KEY_LEFT>,
|
||||
<0xea KEY_RIGHT>,
|
||||
<0xeb KEY_VOLUMEDOWN>,
|
||||
<0xef KEY_VOLUMEUP>,
|
||||
<0xf7 KEY_MUTE>,
|
||||
<0xe7 KEY_POWER>,
|
||||
<0xfc KEY_POWER>,
|
||||
<0xa9 KEY_VOLUMEDOWN>,
|
||||
<0xa8 KEY_PLAYPAUSE>,
|
||||
<0xe0 KEY_VOLUMEDOWN>,
|
||||
<0xa5 KEY_VOLUMEDOWN>,
|
||||
<0xab 183>,
|
||||
<0xb7 388>,
|
||||
<0xe8 388>,
|
||||
<0xf8 184>,
|
||||
<0xaf 185>,
|
||||
<0xed KEY_VOLUMEDOWN>,
|
||||
<0xee 186>,
|
||||
<0xb3 KEY_VOLUMEDOWN>,
|
||||
<0xf1 KEY_VOLUMEDOWN>,
|
||||
<0xf2 KEY_VOLUMEDOWN>,
|
||||
<0xf3 KEY_SEARCH>,
|
||||
<0xb4 KEY_VOLUMEDOWN>,
|
||||
<0xa4 KEY_SETUP>,
|
||||
<0xbe KEY_SEARCH>;
|
||||
};
|
||||
|
||||
ir_key3 {
|
||||
rockchip,usercode = <0x1dcc>;
|
||||
rockchip,key_table =
|
||||
<0xee KEY_REPLY>,
|
||||
<0xf0 KEY_BACK>,
|
||||
<0xf8 KEY_UP>,
|
||||
<0xbb KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xed KEY_RIGHT>,
|
||||
<0xfc KEY_HOME>,
|
||||
<0xf1 KEY_VOLUMEUP>,
|
||||
<0xfd KEY_VOLUMEDOWN>,
|
||||
<0xb7 KEY_SEARCH>,
|
||||
<0xff KEY_POWER>,
|
||||
<0xf3 KEY_MUTE>,
|
||||
<0xbf KEY_MENU>,
|
||||
<0xf9 0x191>,
|
||||
<0xf5 0x192>,
|
||||
<0xb3 388>,
|
||||
<0xbe KEY_1>,
|
||||
<0xba KEY_2>,
|
||||
<0xb2 KEY_3>,
|
||||
<0xbd KEY_4>,
|
||||
<0xf9 KEY_5>,
|
||||
<0xb1 KEY_6>,
|
||||
<0xfc KEY_7>,
|
||||
<0xf8 KEY_8>,
|
||||
<0xb0 KEY_9>,
|
||||
<0xb6 KEY_0>,
|
||||
<0xb5 KEY_BACKSPACE>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdio {
|
||||
bus-width = <4>;
|
||||
max_frequency = <50000000>;
|
||||
cap-sd-highspeed;
|
||||
supports-sdio;
|
||||
ignore-pm-notify;
|
||||
keep-power-in-suspend;
|
||||
supports-rk912;
|
||||
/delete-property/ non-removable;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
|
||||
|
||||
//status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
disable-wp;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
|
||||
supports-sd;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sfc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tve {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vdpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpu_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -374,6 +374,10 @@
|
||||
|
||||
&i2s {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2s_sclk
|
||||
&i2s_lrclktx
|
||||
&i2s_sdo
|
||||
&i2s_sdi>;
|
||||
};
|
||||
|
||||
&mpp_srv {
|
||||
|
||||
@@ -408,6 +408,20 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spdif_tx: spdif-tx@10204000 {
|
||||
compatible = "rockchip,rk3066-spdif";
|
||||
reg = <0x10204000 0x1000>;
|
||||
clocks = <&cru SCLK_SPDIF>, <&cru SCLK_SPDIF>;
|
||||
clock-names = "mclk", "hclk";
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&pdma 13>;
|
||||
dma-names = "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spdif_out>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfc: sfc@10208000 {
|
||||
compatible = "rockchip,sfc";
|
||||
reg = <0x10208000 0x200>;
|
||||
@@ -488,7 +502,12 @@
|
||||
resets = <&cru SRST_I2S>;
|
||||
reset-names = "reset-m";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s_bus>;
|
||||
pinctrl-0 = <&i2s_mclk
|
||||
&i2s_sclk
|
||||
&i2s_lrclkrx
|
||||
&i2s_lrclktx
|
||||
&i2s_sdo
|
||||
&i2s_sdi>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -538,7 +557,7 @@
|
||||
};
|
||||
|
||||
acodec: acodec-ana@20030000 {
|
||||
compatible = "rk3036-codec";
|
||||
compatible = "rockchip,rk3036-codec";
|
||||
reg = <0x20030000 0x4000>;
|
||||
rockchip,grf = <&grf>;
|
||||
clock-names = "acodec_pclk";
|
||||
@@ -570,25 +589,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_sound: hdmi-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,hdmi";
|
||||
simple-audio-card,widgets = "Headphone", "Out Jack",
|
||||
"Line", "In Jack";
|
||||
status = "disabled";
|
||||
|
||||
simple-audio-card,dai-link {
|
||||
format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
cpu {
|
||||
sound-dai = <&i2s>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer: timer@20044000 {
|
||||
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
|
||||
reg = <0x20044000 0x20>;
|
||||
@@ -897,6 +897,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
spdif_tx {
|
||||
spdif_out: spdif-out {
|
||||
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
emac {
|
||||
emac_xfer: emac-xfer {
|
||||
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
|
||||
@@ -937,13 +943,23 @@
|
||||
};
|
||||
|
||||
i2s {
|
||||
i2s_bus: i2s-bus {
|
||||
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
|
||||
<1 RK_PA1 1 &pcfg_pull_default>,
|
||||
<1 RK_PA2 1 &pcfg_pull_default>,
|
||||
<1 RK_PA3 1 &pcfg_pull_default>,
|
||||
<1 RK_PA4 1 &pcfg_pull_default>,
|
||||
<1 RK_PA5 1 &pcfg_pull_default>;
|
||||
i2s_mclk: i2s-mclk {
|
||||
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>;
|
||||
};
|
||||
i2s_sclk: i2s-sclk {
|
||||
rockchip,pins = <1 RK_PA1 1 &pcfg_pull_default>;
|
||||
};
|
||||
i2s_lrclkrx: i2s-lrclkrx {
|
||||
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
|
||||
};
|
||||
i2s_lrclktx: i2s-lrclktx {
|
||||
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
|
||||
};
|
||||
i2s_sdo: i2s-sdo {
|
||||
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>;
|
||||
};
|
||||
i2s_sdi: i2s-sdi {
|
||||
rockchip,pins = <1 RK_PA5 1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -127,6 +127,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
@@ -925,13 +926,13 @@
|
||||
&sdmmc {
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
supports-sd;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
vmmc-supply = <&vcc_sdmmc>;
|
||||
broken-cd;
|
||||
card-detect-delay = <800>;
|
||||
ignore-pm-notify;
|
||||
keep-power-in-suspend;
|
||||
cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_det>;
|
||||
rockchip,default-sample-phase=<90>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@@ -169,6 +169,10 @@
|
||||
<&qos_vip0>;
|
||||
};
|
||||
|
||||
&sdmmc_pwren {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -160,6 +160,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP-SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -832,12 +832,11 @@
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
clock-freq-min-max = <400000 50000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
max-frequency = <50000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
dmas = <&pdma 10>;
|
||||
dma-names = "rx-tx";
|
||||
num-slots = <1>;
|
||||
fifo-depth = <0x100>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
@@ -1466,6 +1465,10 @@
|
||||
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sdmmc_det: sdmmc-det {
|
||||
rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
@@ -102,6 +102,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -82,6 +82,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -74,6 +74,7 @@
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */
|
||||
cpu { sound-dai = <&spdif>; };
|
||||
codec { sound-dai = <&spdif_out>; };
|
||||
|
||||
@@ -130,6 +130,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -64,6 +64,7 @@
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */
|
||||
cpu { sound-dai = <&spdif>; };
|
||||
codec { sound-dai = <&spdif_out>; };
|
||||
|
||||
@@ -154,7 +154,7 @@
|
||||
rockchip,pvtm-error = <1000>;
|
||||
rockchip,pvtm-ref-temp = <35>;
|
||||
rockchip,pvtm-temp-prop = <(-18) (-18)>;
|
||||
rockchip,thermal-zone = "soc-thermal";
|
||||
rockchip,thermal-zone = "cpu-thermal";
|
||||
|
||||
opp-126000000 {
|
||||
opp-hz = /bits/ 64 <126000000>;
|
||||
@@ -611,7 +611,7 @@
|
||||
thermal-sensors = <&tsadc 0>;
|
||||
};
|
||||
|
||||
cpu_thermal: cpu_thermal {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <100>; /* milliseconds */
|
||||
polling-delay = <5000>; /* milliseconds */
|
||||
|
||||
@@ -725,7 +725,7 @@
|
||||
|
||||
usb_host0_ehci: usb@ff500000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xff500000 0x0 0x20000>;
|
||||
reg = <0x0 0xff500000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
|
||||
clock-names = "usbhost", "utmi";
|
||||
@@ -1341,6 +1341,7 @@
|
||||
power-domains = <&power RK3288_PD_VIO>;
|
||||
resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
|
||||
reset-names = "core", "axi", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vopb: vop@ff930000 {
|
||||
@@ -1786,6 +1787,10 @@
|
||||
3 61
|
||||
>;
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <950000>;
|
||||
|
||||
@@ -81,6 +81,7 @@
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-tx-sound";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_tx>;
|
||||
};
|
||||
|
||||
@@ -112,6 +112,7 @@
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-tx-sound";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_tx>;
|
||||
};
|
||||
|
||||
@@ -108,6 +108,7 @@
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-tx-sound";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_tx>;
|
||||
};
|
||||
|
||||
@@ -334,8 +334,10 @@ CONFIG_SND_SOC_ROCKCHIP=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_RT5645=y
|
||||
CONFIG_SND_SOC_ES8311=y
|
||||
CONFIG_SND_SOC_ES8323=y
|
||||
CONFIG_SND_SOC_ES8396=y
|
||||
CONFIG_SND_SOC_INNO_RK3036=y
|
||||
CONFIG_SND_SOC_RK312X=y
|
||||
CONFIG_SND_SOC_RT5616=y
|
||||
CONFIG_SND_SOC_RT5640=y
|
||||
|
||||
@@ -73,6 +73,23 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb2lvds.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-pdm-mic-array.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10-dsm.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-rk817-tablet-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb
|
||||
@@ -95,6 +112,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-spi-nor.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb
|
||||
|
||||
@@ -1215,38 +1215,33 @@
|
||||
cru: clock-controller@ff2b0000 {
|
||||
compatible = "rockchip,px30-cru";
|
||||
reg = <0x0 0xff2b0000 0x0 0x1000>;
|
||||
clocks = <&xin24m>, <&pmucru PLL_GPLL>;
|
||||
clock-names = "xin24m", "gpll";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
assigned-clocks = <&cru PLL_NPLL>,
|
||||
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
|
||||
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
|
||||
<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
|
||||
|
||||
assigned-clock-rates = <1188000000>,
|
||||
<200000000>, <200000000>,
|
||||
<150000000>, <150000000>,
|
||||
<100000000>, <200000000>;
|
||||
assigned-clocks = <&cru PLL_NPLL>;
|
||||
assigned-clock-rates = <1188000000>;
|
||||
};
|
||||
|
||||
pmucru: clock-controller@ff2bc000 {
|
||||
compatible = "rockchip,px30-pmucru";
|
||||
reg = <0x0 0xff2bc000 0x0 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
assigned-clocks =
|
||||
<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
|
||||
<&pmucru SCLK_WIFI_PMU>;
|
||||
<&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
|
||||
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
|
||||
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
|
||||
<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
|
||||
assigned-clock-rates =
|
||||
<1200000000>, <100000000>,
|
||||
<26000000>;
|
||||
<26000000>, <600000000>,
|
||||
<200000000>, <200000000>,
|
||||
<150000000>, <150000000>,
|
||||
<100000000>, <200000000>;
|
||||
};
|
||||
|
||||
usb2phy_grf: syscon@ff2c0000 {
|
||||
|
||||
@@ -256,7 +256,7 @@
|
||||
clock-frequency = <400000>;
|
||||
|
||||
vdd_npu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -139,6 +139,7 @@
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-tx-sound";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_tx>;
|
||||
};
|
||||
|
||||
@@ -112,6 +112,7 @@
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-rx-sound";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_rx>;
|
||||
};
|
||||
|
||||
@@ -464,37 +464,36 @@
|
||||
};
|
||||
|
||||
usb2phy_grf: syscon@ff008000 {
|
||||
compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
|
||||
"simple-mfd";
|
||||
compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff008000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy: usb2-phy@100 {
|
||||
u2phy: usb2phy@100 {
|
||||
compatible = "rockchip,rk3308-usb2phy";
|
||||
reg = <0x100 0x10>;
|
||||
clocks = <&cru SCLK_USBPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&cru USB480M>;
|
||||
assigned-clock-parents = <&u2phy>;
|
||||
clocks = <&cru SCLK_USBPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "otg-bvalid", "otg-id",
|
||||
"linestate";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u2phy_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "linestate";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -573,7 +572,7 @@
|
||||
};
|
||||
|
||||
wdt: watchdog@ff080000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
|
||||
reg = <0x0 0xff080000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_WDT>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -950,33 +949,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
amba: bus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dmac0: dma-controller@ff2c0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xff2c0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMAC0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@ff2c0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xff2c0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMAC0>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@ff2d0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xff2d0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMAC1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
dmac1: dma-controller@ff2d0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xff2d0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_DMAC1>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
vop: vop@ff2e0000 {
|
||||
@@ -1212,7 +1204,8 @@
|
||||
};
|
||||
|
||||
usb20_otg: usb@ff400000 {
|
||||
compatible = "rockchip,rk3066-usb", "snps,dwc2";
|
||||
compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
reg = <0x0 0xff400000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG>;
|
||||
@@ -1291,6 +1284,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand-controller@ff4b0000 {
|
||||
compatible = "rockchip,rk3308-nfc",
|
||||
"rockchip,rv1108-nfc";
|
||||
reg = <0x0 0xff4b0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
|
||||
clock-names = "ahb", "nfc";
|
||||
assigned-clocks = <&cru SCLK_NANDC>;
|
||||
assigned-clock-rates = <150000000>;
|
||||
pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
|
||||
&flash_rdn &flash_rdy &flash_wrn>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nandc: nandc@ff4b0000 {
|
||||
compatible = "rockchip,rk-nandc";
|
||||
reg = <0x0 0xff4b0000 0x0 0x4000>;
|
||||
@@ -1301,21 +1309,9 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfc: sfc@ff4c0000 {
|
||||
compatible = "rockchip,sfc";
|
||||
reg = <0x0 0xff4c0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
||||
clock-names = "clk_sfc", "hclk_sfc";
|
||||
assigned-clocks = <&cru SCLK_SFC>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac: ethernet@ff4e0000 {
|
||||
compatible = "rockchip,rk3308-mac";
|
||||
reg = <0x0 0xff4e0000 0x0 0x10000>;
|
||||
rockchip,grf = <&grf>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
|
||||
@@ -1331,16 +1327,28 @@
|
||||
pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
|
||||
resets = <&cru SRST_MAC_A>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfc: spi@ff4c0000 {
|
||||
compatible = "rockchip,sfc";
|
||||
reg = <0x0 0xff4c0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
||||
clock-names = "clk_sfc", "hclk_sfc";
|
||||
assigned-clocks = <&cru SCLK_SFC>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0x0 0xff500000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,boost = <&cpu_boost>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru SCLK_RTC32K>;
|
||||
assigned-clock-rates = <32768>;
|
||||
};
|
||||
|
||||
@@ -125,7 +125,7 @@
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif-tx-sound";
|
||||
status = "disabled";
|
||||
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_tx>;
|
||||
};
|
||||
|
||||
@@ -55,7 +55,7 @@
|
||||
spdif-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SPDIF";
|
||||
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -87,6 +87,7 @@
|
||||
spdif-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip-spdif";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -59,6 +59,7 @@
|
||||
spdif-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip-spdif";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -97,33 +97,26 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "rockchip,rk809-codec";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Headphone", "Headphone Jack";
|
||||
simple-audio-card,routing =
|
||||
"Mic Jack", "MICBIAS1",
|
||||
"IN1P", "Mic Jack",
|
||||
"Headphone Jack", "HPOL",
|
||||
"Headphone Jack", "HPOR";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_2ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809_codec>;
|
||||
};
|
||||
};
|
||||
|
||||
rk_headset: rk-headset {
|
||||
compatible = "rockchip_headset";
|
||||
headset_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
rk809_sound: rk809-sound {
|
||||
status = "okay";
|
||||
compatible = "rockchip,multicodecs-card";
|
||||
rockchip,card-name = "rockchip-rk809";
|
||||
hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "adc-detect";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
poll-interval = <100>;
|
||||
rockchip,format = "i2s";
|
||||
rockchip,mclk-fs = <256>;
|
||||
rockchip,cpu = <&i2s1_2ch>;
|
||||
rockchip,codec = <&rk809_codec>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_det>;
|
||||
io-channels = <&saradc 1>;
|
||||
play-pause-key {
|
||||
label = "playpause";
|
||||
linux,code = <KEY_PLAYPAUSE>;
|
||||
press-threshold-microvolt = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
|
||||
@@ -33,6 +33,15 @@
|
||||
compatible = "rockchip,drm-logo";
|
||||
reg = <0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
|
||||
ramoops: ramoops@110000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0x0 0x110000 0x0 0xf0000>;
|
||||
record-size = <0x20000>;
|
||||
console-size = <0x80000>;
|
||||
ftrace-size = <0x00000>;
|
||||
pmsg-size = <0x50000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -383,8 +383,8 @@
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@10 {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_cpu: tcs4526@10 {
|
||||
compatible = "tcs,tcs4526";
|
||||
reg = <0x10>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
pinctrl-0 = <&vsel_gpio>;
|
||||
|
||||
@@ -339,8 +339,8 @@
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@10 {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_cpu: tcs4526@10 {
|
||||
compatible = "tcs,tcs4526";
|
||||
reg = <0x10>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
pinctrl-0 = <&vsel_gpio>;
|
||||
|
||||
@@ -89,6 +89,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -138,6 +138,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
@@ -444,8 +445,8 @@
|
||||
i2c-scl-falling-time-ns = <4>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
vdd_cpu_b: tcs452x@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_cpu_b: tcs4525@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
@@ -464,8 +465,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: tcs452x@10 {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_gpu: tcs4526@10 {
|
||||
compatible = "tcs,tcs4526";
|
||||
reg = <0x10>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
@@ -874,6 +875,19 @@
|
||||
source-pdos =
|
||||
<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
|
||||
|
||||
displayport = <&cdn_dp>;
|
||||
|
||||
altmodes {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
altmode@0 {
|
||||
reg = <0>;
|
||||
svid = <0xff01>;
|
||||
vdo = <0xffffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@@ -884,6 +898,12 @@
|
||||
remote-endpoint = <&tcphy0_orientation_switch>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dp_mode_sw: endpoint {
|
||||
remote-endpoint = <&tcphy_dp_altmode_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1209,6 +1229,7 @@
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
|
||||
svid = <0xff01>;
|
||||
orientation-switch;
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
@@ -1217,6 +1238,10 @@
|
||||
reg = <0>;
|
||||
remote-endpoint = <&usbc0_orien_sw>;
|
||||
};
|
||||
tcphy_dp_altmode_switch: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&dp_mode_sw>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -173,6 +173,7 @@
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -215,6 +215,7 @@
|
||||
status = "okay";
|
||||
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -159,6 +159,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -204,6 +204,7 @@
|
||||
spdif-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,spdif";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -122,6 +122,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -89,6 +89,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
@@ -713,8 +713,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: tcs452x@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_cpu_b: tcs4525@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
@@ -733,8 +733,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: tcs452x@10 {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_gpu: tcs4526@10 {
|
||||
compatible = "tcs,tcs4526";
|
||||
reg = <0x10>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -634,8 +634,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: tcs452x@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_cpu_b: tcs4525@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
@@ -654,8 +654,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: tcs452x@10 {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_gpu: tcs4526@10 {
|
||||
compatible = "tcs,tcs4526";
|
||||
reg = <0x10>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -628,8 +628,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: tcs452x@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_cpu_b: tcs4525@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
@@ -648,8 +648,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: tcs452x@10 {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_gpu: tcs4526@10 {
|
||||
compatible = "tcs,tcs4526";
|
||||
reg = <0x10>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -72,8 +72,8 @@
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
vdd_npu: tcs452x@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
vdd_npu: tcs4525@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -78,6 +78,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_8ch>;
|
||||
};
|
||||
|
||||
@@ -7,29 +7,6 @@
|
||||
#include "rk3528-evb1-ddr4-v10.dtsi"
|
||||
#include "rk3528-android.dtsi"
|
||||
|
||||
/{
|
||||
firmware {
|
||||
android {
|
||||
compatible = "android,firmware";
|
||||
boot_devices = "ffbf0000.mmc";
|
||||
vbmeta {
|
||||
compatible = "android,vbmeta";
|
||||
parts = "vbmeta,boot,system,vendor,dtbo";
|
||||
};
|
||||
fstab {
|
||||
compatible = "android,fstab";
|
||||
vendor {
|
||||
compatible = "android,vendor";
|
||||
dev = "/dev/block/by-name/vendor";
|
||||
type = "ext4";
|
||||
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
|
||||
fsmgr_flags = "wait,avb";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -7,25 +7,3 @@
|
||||
#include "rk3528-evb2-ddr3-v10.dtsi"
|
||||
#include "rk3528-android.dtsi"
|
||||
|
||||
/{
|
||||
firmware {
|
||||
android {
|
||||
compatible = "android,firmware";
|
||||
boot_devices = "ffbf0000.mmc";
|
||||
vbmeta {
|
||||
compatible = "android,vbmeta";
|
||||
parts = "vbmeta,boot,system,vendor,dtbo";
|
||||
};
|
||||
fstab {
|
||||
compatible = "android,fstab";
|
||||
vendor {
|
||||
compatible = "android,vendor";
|
||||
dev = "/dev/block/by-name/vendor";
|
||||
type = "ext4";
|
||||
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
|
||||
fsmgr_flags = "wait,avb";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -7,29 +7,6 @@
|
||||
#include "rk3528-evb3-lp4x-v10.dtsi"
|
||||
#include "rk3528-android.dtsi"
|
||||
|
||||
/{
|
||||
firmware {
|
||||
android {
|
||||
compatible = "android,firmware";
|
||||
boot_devices = "ffbf0000.mmc";
|
||||
vbmeta {
|
||||
compatible = "android,vbmeta";
|
||||
parts = "vbmeta,boot,system,vendor,dtbo";
|
||||
};
|
||||
fstab {
|
||||
compatible = "android,fstab";
|
||||
vendor {
|
||||
compatible = "android,vendor";
|
||||
dev = "/dev/block/by-name/vendor";
|
||||
type = "ext4";
|
||||
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
|
||||
fsmgr_flags = "wait,avb";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pdm {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pdm_clk1
|
||||
|
||||
@@ -7,27 +7,9 @@
|
||||
#include "rk3528-evb1-ddr4-v10.dtsi"
|
||||
#include "rk3528-android.dtsi"
|
||||
|
||||
/{
|
||||
firmware {
|
||||
android {
|
||||
compatible = "android,firmware";
|
||||
boot_devices = "ffbf0000.mmc";
|
||||
vbmeta {
|
||||
compatible = "android,vbmeta";
|
||||
parts = "vbmeta,boot,system,vendor,dtbo";
|
||||
};
|
||||
fstab {
|
||||
compatible = "android,fstab";
|
||||
vendor {
|
||||
compatible = "android,vendor";
|
||||
dev = "/dev/block/by-name/vendor";
|
||||
type = "ext4";
|
||||
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
|
||||
fsmgr_flags = "wait,avb";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
/ {
|
||||
model = "Rockchip rk3528 evb4 board";
|
||||
compatible = "rockchip,rk3528-evb4-ddr4-v10", "rockchip,rk3528";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
|
||||
@@ -10,27 +10,7 @@
|
||||
#include "rk3528-android.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3528 IOTEST LP3 V10 Board";
|
||||
model = "Rockchip rk3528 iotest board";
|
||||
compatible = "rockchip,rk3528-iotest-lp3-v10", "rockchip,rk3528";
|
||||
|
||||
firmware {
|
||||
android {
|
||||
compatible = "android,firmware";
|
||||
boot_devices = "ffbf0000.mmc";
|
||||
vbmeta {
|
||||
compatible = "android,vbmeta";
|
||||
parts = "vbmeta,boot,system,vendor,dtbo";
|
||||
};
|
||||
fstab {
|
||||
compatible = "android,fstab";
|
||||
vendor {
|
||||
compatible = "android,vendor";
|
||||
dev = "/dev/block/by-name/vendor";
|
||||
type = "ext4";
|
||||
mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
|
||||
fsmgr_flags = "wait,avb";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -52,6 +52,54 @@
|
||||
spi2 = &sfc;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
xin24m: xin24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
};
|
||||
|
||||
mclkin_sai0: mclkin-sai0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "i2s0_mclkin";
|
||||
};
|
||||
|
||||
mclkin_sai1: mclkin-sai1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "i2s1_mclkin";
|
||||
};
|
||||
|
||||
mclkout_sai0: mclkout-sai0@ff340014 {
|
||||
compatible = "rockchip,clk-out";
|
||||
reg = <0 0xff340014 0 0x4>;
|
||||
clocks = <&cru MCLK_SAI_I2S0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk_sai0_to_io";
|
||||
rockchip,bit-shift = <1>;
|
||||
rockchip,bit-set-to-disable;
|
||||
};
|
||||
|
||||
mclkout_sai1: mclkout-sai1@ff320004 {
|
||||
compatible = "rockchip,clk-out";
|
||||
reg = <0 0xff320004 0 0x4>;
|
||||
clocks = <&cru MCLK_SAI_I2S1>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk_sai1_to_io";
|
||||
rockchip,bit-shift = <14>;
|
||||
rockchip,bit-set-to-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
@@ -144,8 +192,8 @@
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
nvmem-cells = <&cpu_leakage>;
|
||||
nvmem-cell-names = "leakage";
|
||||
nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>;
|
||||
nvmem-cell-names = "leakage", "opp-info";
|
||||
|
||||
rockchip,video-4k-freq = <1200000>;
|
||||
rockchip,pvtm-voltage-sel = <
|
||||
@@ -375,13 +423,6 @@
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
xin24m: xin24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
};
|
||||
|
||||
scmi_shmem: scmi-shmem@10f000 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x0010f000 0x0 0x100>;
|
||||
@@ -882,8 +923,8 @@
|
||||
gpu_opp_table: gpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
nvmem-cells = <&gpu_leakage>;
|
||||
nvmem-cell-names = "leakage";
|
||||
nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>;
|
||||
nvmem-cell-names = "leakage", "opp-info";
|
||||
|
||||
rockchip,pvtm-voltage-sel = <
|
||||
0 820 0
|
||||
@@ -1979,10 +2020,10 @@
|
||||
compatible = "rockchip,crypto-v4";
|
||||
reg = <0x0 0xffc40000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
|
||||
<&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
|
||||
clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>,
|
||||
<&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
|
||||
clock-names = "aclk", "hclk", "sclk", "pka";
|
||||
assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
|
||||
assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
|
||||
assigned-clock-rates = <300000000>, <300000000>;
|
||||
resets = <&cru SRST_RESETN_CORE_CRYPTO>;
|
||||
reset-names = "crypto-rst";
|
||||
@@ -1993,7 +2034,7 @@
|
||||
compatible = "rockchip,rkrng";
|
||||
reg = <0x0 0xffc50000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_TRNG_NS>;
|
||||
clocks = <&scmi_clk SCMI_HCLK_TRNG>;
|
||||
clock-names = "hclk_trng";
|
||||
resets = <&cru SRST_HRESETN_TRNG_NS>;
|
||||
reset-names = "reset";
|
||||
@@ -2039,6 +2080,15 @@
|
||||
macphy_txlevel: macphy-txlevel@2e {
|
||||
reg = <0x2e 0x2>;
|
||||
};
|
||||
cpu_opp_info: cpu-opp-info@32 {
|
||||
reg = <0x32 0x6>;
|
||||
};
|
||||
gpu_opp_info: gpu-opp-info@38 {
|
||||
reg = <0x38 0x6>;
|
||||
};
|
||||
dmc_opp_info: dmc-opp-info@3e {
|
||||
reg = <0x3e 0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
dmac: dma-controller@ffd60000 {
|
||||
|
||||
58
arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
Normal file
58
arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
Normal file
@@ -0,0 +1,58 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/ {
|
||||
rockchip_amp: rockchip-amp {
|
||||
compatible = "rockchip,mcu-amp";
|
||||
clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>,
|
||||
<&cru PCLK_MAILBOX>, <&cru PCLK_INTC>,
|
||||
<&cru SCLK_UART7>, <&cru PCLK_UART7>,
|
||||
<&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rpmsg: rpmsg@a0000000 {
|
||||
compatible = "rockchip,rk3562-rpmsg";
|
||||
mbox-names = "rpmsg-rx", "rpmsg-tx";
|
||||
mboxes = <&mailbox 0 &mailbox 3>;
|
||||
rockchip,vdev-nums = <1>;
|
||||
rockchip,link-id = <0x04>;
|
||||
reg = <0x0 0xa0000000 0x0 0x20000>;
|
||||
memory-region = <&rpmsg_dma_reserved>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* mcu address */
|
||||
mcu_reserved: mcu@8200000 {
|
||||
reg = <0x0 0x8200000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rpmsg_reserved: rpmsg@a0000000 {
|
||||
reg = <0x0 0xa0000000 0x0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rpmsg_dma_reserved: rpmsg-dma@a0400000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0xa0400000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox {
|
||||
status = "okay";
|
||||
};
|
||||
39
arch/arm64/boot/dts/rockchip/rk3562-android.dtsi
Normal file
39
arch/arm64/boot/dts/rockchip/rk3562-android.dtsi
Normal file
@@ -0,0 +1,39 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen: chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0";
|
||||
};
|
||||
|
||||
fiq-debugger {
|
||||
compatible = "rockchip,fiq-debugger";
|
||||
rockchip,serial-id = <0>;
|
||||
rockchip,wake-irq = <0>;
|
||||
/* If enable uart uses irq instead of fiq */
|
||||
rockchip,irq-mode-enable = <1>;
|
||||
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
|
||||
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee: optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vop {
|
||||
support-multi-area;
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
584
arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi
Normal file
584
arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi
Normal file
@@ -0,0 +1,584 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/drm_mipi_dsi.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
/ {
|
||||
adc_keys: adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc0 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
poll-interval = <100>;
|
||||
|
||||
vol-up-key {
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
label = "volume up";
|
||||
press-threshold-microvolt = <17000>;
|
||||
};
|
||||
|
||||
vol-down-key {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
label = "volume down";
|
||||
press-threshold-microvolt = <414000>;
|
||||
};
|
||||
|
||||
menu-key {
|
||||
linux,code = <KEY_MENU>;
|
||||
label = "menu";
|
||||
press-threshold-microvolt = <800000>;
|
||||
};
|
||||
|
||||
back-key {
|
||||
linux,code = <KEY_BACK>;
|
||||
label = "back";
|
||||
press-threshold-microvolt = <1200000>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm5 0 25000 0>;
|
||||
brightness-levels = <
|
||||
0 20 20 21 21 22 22 23
|
||||
23 24 24 25 25 26 26 27
|
||||
27 28 28 29 29 30 30 31
|
||||
31 32 32 33 33 34 34 35
|
||||
35 36 36 37 37 38 38 39
|
||||
40 41 42 43 44 45 46 47
|
||||
48 49 50 51 52 53 54 55
|
||||
56 57 58 59 60 61 62 63
|
||||
64 65 66 67 68 69 70 71
|
||||
72 73 74 75 76 77 78 79
|
||||
80 81 82 83 84 85 86 87
|
||||
88 89 90 91 92 93 94 95
|
||||
96 97 98 99 100 101 102 103
|
||||
104 105 106 107 108 109 110 111
|
||||
112 113 114 115 116 117 118 119
|
||||
120 121 122 123 124 125 126 127
|
||||
128 129 130 131 132 133 134 135
|
||||
136 137 138 139 140 141 142 143
|
||||
144 145 146 147 148 149 150 151
|
||||
152 153 154 155 156 157 158 159
|
||||
160 161 162 163 164 165 166 167
|
||||
168 169 170 171 172 173 174 175
|
||||
176 177 178 179 180 181 182 183
|
||||
184 185 186 187 188 189 190 191
|
||||
192 193 194 195 196 197 198 199
|
||||
200 201 202 203 204 205 206 207
|
||||
208 209 210 211 212 213 214 215
|
||||
216 217 218 219 220 221 222 223
|
||||
224 225 226 227 228 229 230 231
|
||||
232 233 234 235 236 237 238 239
|
||||
240 241 242 243 244 245 246 247
|
||||
248 249 250 251 252 253 254 255
|
||||
>;
|
||||
default-brightness-level = <200>;
|
||||
};
|
||||
|
||||
pdm_codec: dummy-codec {
|
||||
status = "okay";
|
||||
compatible = "rockchip,dummy-codec";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
pdm_mic_array: pdm-mic-array {
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,pdm-mic-array";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&pdm>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&pdm_codec>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif_out: spdif-out {
|
||||
status = "okay";
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
spdif-sound {
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rk-spdif-sound";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&spdif_out>;
|
||||
};
|
||||
};
|
||||
|
||||
test-power {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vcc3v3_lcd_n: vcc3v3-lcd0-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd_n";
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "disabled";
|
||||
//rockchip,lane-rate = <1000>;
|
||||
dsi_panel: panel@0 {
|
||||
status = "okay";
|
||||
compatible = "simple-panel-dsi";
|
||||
reg = <0>;
|
||||
backlight = <&backlight>;
|
||||
reset-delay-ms = <60>;
|
||||
enable-delay-ms = <60>;
|
||||
prepare-delay-ms = <60>;
|
||||
unprepare-delay-ms = <60>;
|
||||
disable-delay-ms = <60>;
|
||||
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
|
||||
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
|
||||
dsi,format = <MIPI_DSI_FMT_RGB888>;
|
||||
dsi,lanes = <4>;
|
||||
panel-init-sequence = [
|
||||
23 00 02 FE 21
|
||||
23 00 02 04 00
|
||||
23 00 02 00 64
|
||||
23 00 02 2A 00
|
||||
23 00 02 26 64
|
||||
23 00 02 54 00
|
||||
23 00 02 50 64
|
||||
23 00 02 7B 00
|
||||
23 00 02 77 64
|
||||
23 00 02 A2 00
|
||||
23 00 02 9D 64
|
||||
23 00 02 C9 00
|
||||
23 00 02 C5 64
|
||||
23 00 02 01 71
|
||||
23 00 02 27 71
|
||||
23 00 02 51 71
|
||||
23 00 02 78 71
|
||||
23 00 02 9E 71
|
||||
23 00 02 C6 71
|
||||
23 00 02 02 89
|
||||
23 00 02 28 89
|
||||
23 00 02 52 89
|
||||
23 00 02 79 89
|
||||
23 00 02 9F 89
|
||||
23 00 02 C7 89
|
||||
23 00 02 03 9E
|
||||
23 00 02 29 9E
|
||||
23 00 02 53 9E
|
||||
23 00 02 7A 9E
|
||||
23 00 02 A0 9E
|
||||
23 00 02 C8 9E
|
||||
23 00 02 09 00
|
||||
23 00 02 05 B0
|
||||
23 00 02 31 00
|
||||
23 00 02 2B B0
|
||||
23 00 02 5A 00
|
||||
23 00 02 55 B0
|
||||
23 00 02 80 00
|
||||
23 00 02 7C B0
|
||||
23 00 02 A7 00
|
||||
23 00 02 A3 B0
|
||||
23 00 02 CE 00
|
||||
23 00 02 CA B0
|
||||
23 00 02 06 C0
|
||||
23 00 02 2D C0
|
||||
23 00 02 56 C0
|
||||
23 00 02 7D C0
|
||||
23 00 02 A4 C0
|
||||
23 00 02 CB C0
|
||||
23 00 02 07 CF
|
||||
23 00 02 2F CF
|
||||
23 00 02 58 CF
|
||||
23 00 02 7E CF
|
||||
23 00 02 A5 CF
|
||||
23 00 02 CC CF
|
||||
23 00 02 08 DD
|
||||
23 00 02 30 DD
|
||||
23 00 02 59 DD
|
||||
23 00 02 7F DD
|
||||
23 00 02 A6 DD
|
||||
23 00 02 CD DD
|
||||
23 00 02 0E 15
|
||||
23 00 02 0A E9
|
||||
23 00 02 36 15
|
||||
23 00 02 32 E9
|
||||
23 00 02 5F 15
|
||||
23 00 02 5B E9
|
||||
23 00 02 85 15
|
||||
23 00 02 81 E9
|
||||
23 00 02 AD 15
|
||||
23 00 02 A9 E9
|
||||
23 00 02 D3 15
|
||||
23 00 02 CF E9
|
||||
23 00 02 0B 14
|
||||
23 00 02 33 14
|
||||
23 00 02 5C 14
|
||||
23 00 02 82 14
|
||||
23 00 02 AA 14
|
||||
23 00 02 D0 14
|
||||
23 00 02 0C 36
|
||||
23 00 02 34 36
|
||||
23 00 02 5D 36
|
||||
23 00 02 83 36
|
||||
23 00 02 AB 36
|
||||
23 00 02 D1 36
|
||||
23 00 02 0D 6B
|
||||
23 00 02 35 6B
|
||||
23 00 02 5E 6B
|
||||
23 00 02 84 6B
|
||||
23 00 02 AC 6B
|
||||
23 00 02 D2 6B
|
||||
23 00 02 13 5A
|
||||
23 00 02 0F 94
|
||||
23 00 02 3B 5A
|
||||
23 00 02 37 94
|
||||
23 00 02 64 5A
|
||||
23 00 02 60 94
|
||||
23 00 02 8A 5A
|
||||
23 00 02 86 94
|
||||
23 00 02 B2 5A
|
||||
23 00 02 AE 94
|
||||
23 00 02 D8 5A
|
||||
23 00 02 D4 94
|
||||
23 00 02 10 D1
|
||||
23 00 02 38 D1
|
||||
23 00 02 61 D1
|
||||
23 00 02 87 D1
|
||||
23 00 02 AF D1
|
||||
23 00 02 D5 D1
|
||||
23 00 02 11 04
|
||||
23 00 02 39 04
|
||||
23 00 02 62 04
|
||||
23 00 02 88 04
|
||||
23 00 02 B0 04
|
||||
23 00 02 D6 04
|
||||
23 00 02 12 05
|
||||
23 00 02 3A 05
|
||||
23 00 02 63 05
|
||||
23 00 02 89 05
|
||||
23 00 02 B1 05
|
||||
23 00 02 D7 05
|
||||
23 00 02 18 AA
|
||||
23 00 02 14 36
|
||||
23 00 02 42 AA
|
||||
23 00 02 3D 36
|
||||
23 00 02 69 AA
|
||||
23 00 02 65 36
|
||||
23 00 02 8F AA
|
||||
23 00 02 8B 36
|
||||
23 00 02 B7 AA
|
||||
23 00 02 B3 36
|
||||
23 00 02 DD AA
|
||||
23 00 02 D9 36
|
||||
23 00 02 15 74
|
||||
23 00 02 3F 74
|
||||
23 00 02 66 74
|
||||
23 00 02 8C 74
|
||||
23 00 02 B4 74
|
||||
23 00 02 DA 74
|
||||
23 00 02 16 9F
|
||||
23 00 02 40 9F
|
||||
23 00 02 67 9F
|
||||
23 00 02 8D 9F
|
||||
23 00 02 B5 9F
|
||||
23 00 02 DB 9F
|
||||
23 00 02 17 DC
|
||||
23 00 02 41 DC
|
||||
23 00 02 68 DC
|
||||
23 00 02 8E DC
|
||||
23 00 02 B6 DC
|
||||
23 00 02 DC DC
|
||||
23 00 02 1D FF
|
||||
23 00 02 19 03
|
||||
23 00 02 47 FF
|
||||
23 00 02 43 03
|
||||
23 00 02 6E FF
|
||||
23 00 02 6A 03
|
||||
23 00 02 94 FF
|
||||
23 00 02 90 03
|
||||
23 00 02 BC FF
|
||||
23 00 02 B8 03
|
||||
23 00 02 E2 FF
|
||||
23 00 02 DE 03
|
||||
23 00 02 1A 35
|
||||
23 00 02 44 35
|
||||
23 00 02 6B 35
|
||||
23 00 02 91 35
|
||||
23 00 02 B9 35
|
||||
23 00 02 DF 35
|
||||
23 00 02 1B 45
|
||||
23 00 02 45 45
|
||||
23 00 02 6C 45
|
||||
23 00 02 92 45
|
||||
23 00 02 BA 45
|
||||
23 00 02 E0 45
|
||||
23 00 02 1C 55
|
||||
23 00 02 46 55
|
||||
23 00 02 6D 55
|
||||
23 00 02 93 55
|
||||
23 00 02 BB 55
|
||||
23 00 02 E1 55
|
||||
23 00 02 22 FF
|
||||
23 00 02 1E 68
|
||||
23 00 02 4C FF
|
||||
23 00 02 48 68
|
||||
23 00 02 73 FF
|
||||
23 00 02 6F 68
|
||||
23 00 02 99 FF
|
||||
23 00 02 95 68
|
||||
23 00 02 C1 FF
|
||||
23 00 02 BD 68
|
||||
23 00 02 E7 FF
|
||||
23 00 02 E3 68
|
||||
23 00 02 1F 7E
|
||||
23 00 02 49 7E
|
||||
23 00 02 70 7E
|
||||
23 00 02 96 7E
|
||||
23 00 02 BE 7E
|
||||
23 00 02 E4 7E
|
||||
23 00 02 20 97
|
||||
23 00 02 4A 97
|
||||
23 00 02 71 97
|
||||
23 00 02 97 97
|
||||
23 00 02 BF 97
|
||||
23 00 02 E5 97
|
||||
23 00 02 21 B5
|
||||
23 00 02 4B B5
|
||||
23 00 02 72 B5
|
||||
23 00 02 98 B5
|
||||
23 00 02 C0 B5
|
||||
23 00 02 E6 B5
|
||||
23 00 02 25 F0
|
||||
23 00 02 23 E8
|
||||
23 00 02 4F F0
|
||||
23 00 02 4D E8
|
||||
23 00 02 76 F0
|
||||
23 00 02 74 E8
|
||||
23 00 02 9C F0
|
||||
23 00 02 9A E8
|
||||
23 00 02 C4 F0
|
||||
23 00 02 C2 E8
|
||||
23 00 02 EA F0
|
||||
23 00 02 E8 E8
|
||||
23 00 02 24 FF
|
||||
23 00 02 4E FF
|
||||
23 00 02 75 FF
|
||||
23 00 02 9B FF
|
||||
23 00 02 C3 FF
|
||||
23 00 02 E9 FF
|
||||
23 00 02 FE 3D
|
||||
23 00 02 00 04
|
||||
23 00 02 FE 23
|
||||
23 00 02 08 82
|
||||
23 00 02 0A 00
|
||||
23 00 02 0B 00
|
||||
23 00 02 0C 01
|
||||
23 00 02 16 00
|
||||
23 00 02 18 02
|
||||
23 00 02 1B 04
|
||||
23 00 02 19 04
|
||||
23 00 02 1C 81
|
||||
23 00 02 1F 00
|
||||
23 00 02 20 03
|
||||
23 00 02 23 04
|
||||
23 00 02 21 01
|
||||
23 00 02 54 63
|
||||
23 00 02 55 54
|
||||
23 00 02 6E 45
|
||||
23 00 02 6D 36
|
||||
23 00 02 FE 3D
|
||||
23 00 02 55 78
|
||||
23 00 02 FE 20
|
||||
23 00 02 26 30
|
||||
23 00 02 FE 3D
|
||||
23 00 02 20 71
|
||||
23 00 02 50 8F
|
||||
23 00 02 51 8F
|
||||
23 00 02 FE 00
|
||||
23 00 02 35 00
|
||||
05 78 01 11
|
||||
05 1E 01 29
|
||||
];
|
||||
|
||||
panel-exit-sequence = [
|
||||
05 00 01 28
|
||||
05 00 01 10
|
||||
];
|
||||
|
||||
disp_timings0: display-timings {
|
||||
native-mode = <&dsi_timing0>;
|
||||
dsi_timing0: timing0 {
|
||||
clock-frequency = <132000000>;
|
||||
hactive = <1080>;
|
||||
vactive = <1920>;
|
||||
hfront-porch = <15>;
|
||||
hsync-len = <2>;
|
||||
hback-porch = <30>;
|
||||
vfront-porch = <15>;
|
||||
vsync-len = <2>;
|
||||
vback-porch = <15>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
panel_in_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out_panel: endpoint {
|
||||
remote-endpoint = <&panel_in_dsi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
mali-supply = <&vdd_gpu>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
gt1x: gt1x@14 {
|
||||
compatible = "goodix,gt1x";
|
||||
reg = <0x14>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_gpio>;
|
||||
goodix,rst-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
goodix,irq-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
/*
|
||||
* power-supply should switche to vcc3v3_lcd1_n
|
||||
* when mipi panel is connected to dsi1.
|
||||
*/
|
||||
power-supply = <&vcc3v3_lcd_n>;
|
||||
};
|
||||
};
|
||||
|
||||
&jpegd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&jpegd_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mpp_srv {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
touch {
|
||||
touch_gpio: touch-gpio {
|
||||
rockchip,pins =
|
||||
<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu {
|
||||
rknpu-supply = <&vdd_npu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rga2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rga2_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvdec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvdec_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvenc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvenc_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc0 {
|
||||
status = "okay";
|
||||
vref-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
213
arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi
Normal file
213
arch/arm64/boot/dts/rockchip/rk3562-evb1-cam.dtsi
Normal file
@@ -0,0 +1,213 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
vcc_mipicsi0: vcc-mipicsi0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mipicsi0_pwr>;
|
||||
regulator-name = "vcc_mipicsi0";
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&gc8034_out0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
mipi_in_ucam1: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&ov5695_out0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidcphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
dw9714: dw9714@c {
|
||||
compatible = "dongwoon,dw9714";
|
||||
status = "okay";
|
||||
reg = <0x0c>;
|
||||
rockchip,vcm-start-current = <10>;
|
||||
rockchip,vcm-rated-current = <85>;
|
||||
rockchip,vcm-step-mode = <5>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
};
|
||||
|
||||
gc8034: gc8034@37 {
|
||||
compatible = "galaxycore,gc8034";
|
||||
reg = <0x37>;
|
||||
clocks = <&cru CLK_CAM0_OUT2IO>;
|
||||
clock-names = "xvclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camm0_clk0_out>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
avdd-supply = <&vcc2v8_dvp>;
|
||||
dovdd-supply = <&vcc1v8_dvp>;
|
||||
dvdd-supply = <&vcc_mipicsi0>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "RK-CMK-8M-2-v1";
|
||||
rockchip,camera-module-lens-name = "CK8401";
|
||||
lens-focus = <&dw9714>;
|
||||
port {
|
||||
gc8034_out0: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
ov5695: ov5695@36 {
|
||||
compatible = "ovti,ov5695";
|
||||
reg = <0x36>;
|
||||
clocks = <&cru CLK_CAM0_OUT2IO>;
|
||||
clock-names = "xvclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camm0_clk0_out>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
avdd-supply = <&vcc2v8_dvp>;
|
||||
dovdd-supply = <&vcc1v8_dvp>;
|
||||
dvdd-supply = <&vcc_mipicsi0>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "TongJu";
|
||||
rockchip,camera-module-lens-name = "CHT842-MD";
|
||||
port {
|
||||
ov5695_out0: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam1>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&csi2_dphy0_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidcphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
mipi_lvds_sditf: endpoint {
|
||||
remote-endpoint = <&isp_vir0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_vir0 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp_vir0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi_lvds_sditf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
mipicsi0_pwr: mipicsi0-pwr {
|
||||
rockchip,pins =
|
||||
/* camera power en */
|
||||
<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-linux.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
#include "rk3562-amp.dtsi"
|
||||
@@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-linux.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
120
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts
Normal file
120
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-lvds.dts
Normal file
@@ -0,0 +1,120 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
|
||||
|
||||
/ {
|
||||
panel-lvds {
|
||||
compatible = "simple-panel";
|
||||
status = "okay";
|
||||
backlight = <&backlight>;
|
||||
reset-delay-ms = <20>;
|
||||
enable-delay-ms = <20>;
|
||||
prepare-delay-ms = <20>;
|
||||
unprepare-delay-ms = <20>;
|
||||
disable-delay-ms = <20>;
|
||||
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
|
||||
width-mm = <164>;
|
||||
height-mm = <100>;
|
||||
|
||||
power-supply = <&vcc3v3_lcd_n>;
|
||||
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_rst_gpio>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
|
||||
timing0: timing0 {
|
||||
clock-frequency = <27000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hback-porch = <160>;
|
||||
hfront-porch = <160>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <15>;
|
||||
hsync-len = <6>;
|
||||
vsync-len = <5>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
panel_in_lvds: endpoint {
|
||||
remote-endpoint = <&lvds_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&backlight {
|
||||
pwms = <&pwm5 0 25000 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&lvds {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lvds_out_panel: endpoint {
|
||||
remote-endpoint = <&panel_in_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lvds_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
lcd {
|
||||
lcd_rst_gpio: lcd-rst-gpio {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm5 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm5m0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vcc3v3_lcd_n {
|
||||
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,240 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB MCU PANLE DISPLAY Ext Board";
|
||||
compatible = "rockchip,rk3562-evb1-lp4x-v10-mcu-k350c4516t", "rockchip,rk3562";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
status = "okay";
|
||||
pwms = <&pwm9 0 25000 0>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi_in_vp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of pcie2x1 and rgb are multiplexed
|
||||
*/
|
||||
&pcie2x1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
rockchip,data-sync-bypass;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* rgb3x8_pins_m0/rgb3x8_pins_m1 for serial mcu
|
||||
* rgb565_pins for parallel mcu
|
||||
*/
|
||||
pinctrl-0 = <&rgb565_pins>;
|
||||
|
||||
/*
|
||||
* 320x480 RGB/MCU screen K350C4516T
|
||||
*/
|
||||
mcu_panel: mcu-panel {
|
||||
/*
|
||||
* MEDIA_BUS_FMT_RGB888_3X8 for serial mcu
|
||||
* MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu
|
||||
*/
|
||||
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
enable-delay-ms = <20>;
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
reset-value = <0>;
|
||||
reset-delay-ms = <10>;
|
||||
prepare-delay-ms = <20>;
|
||||
unprepare-delay-ms = <20>;
|
||||
disable-delay-ms = <20>;
|
||||
width-mm = <217>;
|
||||
height-mm = <136>;
|
||||
|
||||
// type:0 is cmd, 1 is data
|
||||
panel-init-sequence = [
|
||||
//type delay num val1 val2 val3
|
||||
00 00 01 e0
|
||||
01 00 01 00
|
||||
01 00 01 07
|
||||
01 00 01 0f
|
||||
01 00 01 0d
|
||||
01 00 01 1b
|
||||
01 00 01 0a
|
||||
01 00 01 3c
|
||||
01 00 01 78
|
||||
01 00 01 4a
|
||||
01 00 01 07
|
||||
01 00 01 0e
|
||||
01 00 01 09
|
||||
01 00 01 1b
|
||||
01 00 01 1e
|
||||
01 00 01 0f
|
||||
00 00 01 e1
|
||||
01 00 01 00
|
||||
01 00 01 22
|
||||
01 00 01 24
|
||||
01 00 01 06
|
||||
01 00 01 12
|
||||
01 00 01 07
|
||||
01 00 01 36
|
||||
01 00 01 47
|
||||
01 00 01 47
|
||||
01 00 01 06
|
||||
01 00 01 0a
|
||||
01 00 01 07
|
||||
01 00 01 30
|
||||
01 00 01 37
|
||||
01 00 01 0f
|
||||
|
||||
00 00 01 c0
|
||||
01 00 01 10
|
||||
01 00 01 10
|
||||
|
||||
00 00 01 c1
|
||||
01 00 01 41
|
||||
|
||||
00 00 01 c5
|
||||
01 00 01 00
|
||||
01 00 01 22
|
||||
01 00 01 80
|
||||
|
||||
00 00 01 36
|
||||
01 00 01 48
|
||||
|
||||
00 00 01 3a //interface mode control
|
||||
01 00 01 55 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6)
|
||||
// mcu serial: 77(r1 r3 r6)
|
||||
|
||||
00 00 01 b0 //interface mode control
|
||||
01 00 01 00
|
||||
|
||||
00 00 01 b1 //frame rate 70hz
|
||||
01 00 01 b0
|
||||
01 00 01 11
|
||||
00 00 01 b4
|
||||
01 00 01 02
|
||||
00 00 01 B6 //RGB/MCU Interface Control
|
||||
01 00 01 02 //02 mcu, 32 rgb
|
||||
01 00 01 02
|
||||
|
||||
00 00 01 b7
|
||||
01 00 01 c6
|
||||
|
||||
00 00 01 be
|
||||
01 00 01 00
|
||||
01 00 01 04
|
||||
|
||||
00 00 01 e9
|
||||
01 00 01 00
|
||||
|
||||
00 00 01 f7
|
||||
01 00 01 a9
|
||||
01 00 01 51
|
||||
01 00 01 2c
|
||||
01 00 01 82
|
||||
|
||||
00 78 01 11
|
||||
00 32 01 29
|
||||
00 00 01 2c
|
||||
];
|
||||
|
||||
panel-exit-sequence = [
|
||||
//type delay num val1 val2 val3
|
||||
00 0a 01 28
|
||||
00 78 01 10
|
||||
];
|
||||
|
||||
display-timings {
|
||||
native-mode = <&kd050fwfba002_timing>;
|
||||
|
||||
kd050fwfba002_timing: timing0 {
|
||||
clock-frequency = <80000000>;
|
||||
hactive = <320>;
|
||||
vactive = <480>;
|
||||
hback-porch = <10>;
|
||||
hfront-porch = <5>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <5>;
|
||||
hsync-len = <10>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
rgb_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rgb_out_panel: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of sai0 and backlight are multiplexed
|
||||
*/
|
||||
&sai0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
mcu-timing {
|
||||
mcu-pix-total = <9>;
|
||||
mcu-cs-pst = <1>;
|
||||
mcu-cs-pend = <8>;
|
||||
mcu-rw-pst = <2>;
|
||||
mcu-rw-pend = <5>;
|
||||
|
||||
mcu-hold-mode = <0>; // default set to 0
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB VOP3 RGB24BIT DISPLAY Ext Board";
|
||||
compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A", "rockchip,rk3562";
|
||||
|
||||
panel: panel {
|
||||
compatible = "simple-panel";
|
||||
bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
enable-delay-ms = <20>;
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
reset-value = <0>;
|
||||
reset-delay-ms = <10>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&fx070_dhm11boe_timing>;
|
||||
|
||||
fx070_dhm11boe_timing: timing0 {
|
||||
clock-frequency = <50000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hback-porch = <140>;
|
||||
hfront-porch = <160>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <20>;
|
||||
hsync-len = <20>;
|
||||
vsync-len = <2>; //value range <2~22>
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
pwms = <&pwm9 0 25000 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of gmac0/pcie2x1/pdm_codec and rgb are multiplexed
|
||||
*/
|
||||
&gmac0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pdm_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm9 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm9m0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&rgb666_pins>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
rgb_out_panel: endpoint {
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&route_rgb {
|
||||
status = "okay";
|
||||
connect = <&vp0_out_rgb>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of sai0/vcc_mipicsi0 and rgb are multiplexed
|
||||
*/
|
||||
&sai0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vcc_mipicsi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "disabled";
|
||||
};
|
||||
121
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts
Normal file
121
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb2lvds.dts
Normal file
@@ -0,0 +1,121 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
|
||||
|
||||
/ {
|
||||
panel-rgb {
|
||||
compatible = "simple-panel";
|
||||
status = "okay";
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-ms = <20>;
|
||||
enable-delay-ms = <20>;
|
||||
prepare-delay-ms = <20>;
|
||||
unprepare-delay-ms = <20>;
|
||||
disable-delay-ms = <20>;
|
||||
bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
|
||||
width-mm = <164>;
|
||||
height-mm = <100>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
|
||||
timing0: timing0 {
|
||||
clock-frequency = <50000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hback-porch = <140>;
|
||||
hfront-porch = <160>;
|
||||
vback-porch = <20>;
|
||||
vfront-porch = <12>;
|
||||
hsync-len = <20>;
|
||||
vsync-len = <3>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <0>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
pwms = <&pwm9 0 25000 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of gmac0 and rgb are multiplexed
|
||||
*/
|
||||
&gmac0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&rgb666_pins>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
rgb_out_panel: endpoint {
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rgb_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm9 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm9m0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_rgb {
|
||||
status = "okay";
|
||||
connect = <&vp0_out_rgb>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of sai0 and backlight are multiplexed
|
||||
*/
|
||||
&sai0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "disabled";
|
||||
};
|
||||
17
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-spdif.dts
Normal file
17
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-spdif.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb1-lp4x-v10.dts"
|
||||
|
||||
&spdif_8ch {
|
||||
/* The pin is conflict with sdmmc0 cmd */
|
||||
pinctrl-0 = <&spdifm2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
9
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dts
Normal file
9
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
572
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
Normal file
572
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
Normal file
@@ -0,0 +1,572 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "dt-bindings/usb/pd.h"
|
||||
#include "rk3562.dtsi"
|
||||
#include "rk3562-evb.dtsi"
|
||||
#include "rk3562-evb1-cam.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/sensor-dev.h>
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 EVB1 LP4X V10 Board";
|
||||
compatible = "rockchip,rk3562-evb1-lp4x-v10", "rockchip,rk3562";
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
rk817_sound: rk817-sound {
|
||||
status = "okay";
|
||||
compatible = "rockchip,multicodecs-card";
|
||||
rockchip,card-name = "rockchip-rk817";
|
||||
hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
|
||||
rockchip,format = "i2s";
|
||||
rockchip,mclk-fs = <256>;
|
||||
rockchip,cpu = <&sai0>;
|
||||
rockchip,codec = <&rk817_codec>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_det>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk817 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
post-power-on-delay-ms = <200>;
|
||||
reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie20: vcc3v3-pcie20 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie20";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&dcdc_boost>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_host_pwren>;
|
||||
};
|
||||
|
||||
vbat_3v8: vbat-3v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat_3v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3800000>;
|
||||
regulator-max-microvolt = <3800000>;
|
||||
};
|
||||
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-gpio";
|
||||
enable-active-low;
|
||||
enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_sd_h>;
|
||||
regulator-name = "vcc_sd";
|
||||
states = <3300000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3800000>;
|
||||
regulator-max-microvolt = <3800000>;
|
||||
};
|
||||
|
||||
vdd_gpu: vdd-gpu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm7 0 5000 1>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
pwm-supply = <&vcc_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm6 0 5000 1>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
pwm-supply = <&vcc_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
wifi_chip_type = "ap6275s";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
clocks = <&rk817 1>;
|
||||
clock-names = "ext_clock";
|
||||
//wifi-bt-power-toggle;
|
||||
uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart1m0_rtsn>;
|
||||
pinctrl-1 = <&uart1_gpios>;
|
||||
BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
tx_delay = <0x42>;
|
||||
/* rx_delay = <0x3f>; */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmiim0_miim
|
||||
&rgmiim0_tx_bus2
|
||||
&rgmiim0_rx_bus2
|
||||
&rgmiim0_rgmii_clk
|
||||
&rgmiim0_rgmii_bus
|
||||
ðm0_pins>;
|
||||
|
||||
phy-handle = <&rgmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
usbc0: fusb302@22 {
|
||||
compatible = "fcs,fusb302";
|
||||
reg = <0x22>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbc0_int>;
|
||||
vbus-supply = <&otg_switch>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usbc0_role_sw: endpoint@0 {
|
||||
remote-endpoint = <&dwc3_role_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_con: connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
data-role = "dual";
|
||||
power-role = "dual";
|
||||
try-power-role = "sink";
|
||||
op-sink-microwatt = <1000000>;
|
||||
sink-pdos =
|
||||
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
|
||||
source-pdos =
|
||||
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
mpu6500_acc: mpu_acc@68 {
|
||||
compatible = "mpu6500_acc";
|
||||
reg = <0x68>;
|
||||
irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_EDGE_RISING>;
|
||||
irq_enable = <0>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_ACCEL>;
|
||||
layout = <3>;
|
||||
};
|
||||
|
||||
mpu6500_gyro: mpu_gyro@68 {
|
||||
compatible = "mpu6500_gyro";
|
||||
reg = <0x68>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_GYROSCOPE>;
|
||||
layout = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy_pu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi_panel {
|
||||
power-supply = <&vcc3v3_lcd_n>;
|
||||
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_rst_gpio>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
|
||||
assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
|
||||
compatible = "rockchip,remotectl-pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3m0_pins>;
|
||||
assigned-clocks = <&cru CLK_PMU1_PWM0>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
remote_pwm_id = <3>;
|
||||
handle_cpu_id = <1>;
|
||||
remote_support_psci = <1>;
|
||||
|
||||
ir_key1 {
|
||||
rockchip,usercode = <0x4040>;
|
||||
rockchip,key_table =
|
||||
<0xf2 KEY_REPLY>,
|
||||
<0xba KEY_BACK>,
|
||||
<0xf4 KEY_UP>,
|
||||
<0xf1 KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xee KEY_RIGHT>,
|
||||
<0xbd KEY_HOME>,
|
||||
<0xea KEY_VOLUMEUP>,
|
||||
<0xe3 KEY_VOLUMEDOWN>,
|
||||
<0xe2 KEY_SEARCH>,
|
||||
<0xb2 KEY_POWER>,
|
||||
<0xbc KEY_MUTE>,
|
||||
<0xec KEY_MENU>,
|
||||
<0xbf 0x190>,
|
||||
<0xe0 0x191>,
|
||||
<0xe1 0x192>,
|
||||
<0xe9 183>,
|
||||
<0xe6 248>,
|
||||
<0xe8 185>,
|
||||
<0xe7 186>,
|
||||
<0xf0 388>,
|
||||
<0xbe 0x175>;
|
||||
};
|
||||
|
||||
ir_key2 {
|
||||
rockchip,usercode = <0xff00>;
|
||||
rockchip,key_table =
|
||||
<0xf9 KEY_HOME>,
|
||||
<0xbf KEY_BACK>,
|
||||
<0xfb KEY_MENU>,
|
||||
<0xaa KEY_REPLY>,
|
||||
<0xb9 KEY_UP>,
|
||||
<0xe9 KEY_DOWN>,
|
||||
<0xb8 KEY_LEFT>,
|
||||
<0xea KEY_RIGHT>,
|
||||
<0xeb KEY_VOLUMEDOWN>,
|
||||
<0xef KEY_VOLUMEUP>,
|
||||
<0xf7 KEY_MUTE>,
|
||||
<0xe7 KEY_POWER>,
|
||||
<0xfc KEY_POWER>,
|
||||
<0xa9 KEY_VOLUMEDOWN>,
|
||||
<0xa8 KEY_VOLUMEDOWN>,
|
||||
<0xe0 KEY_VOLUMEDOWN>,
|
||||
<0xa5 KEY_VOLUMEDOWN>,
|
||||
<0xab 183>,
|
||||
<0xb7 388>,
|
||||
<0xe8 388>,
|
||||
<0xf8 184>,
|
||||
<0xaf 185>,
|
||||
<0xed KEY_VOLUMEDOWN>,
|
||||
<0xee 186>,
|
||||
<0xb3 KEY_VOLUMEDOWN>,
|
||||
<0xf1 KEY_VOLUMEDOWN>,
|
||||
<0xf2 KEY_VOLUMEDOWN>,
|
||||
<0xf3 KEY_SEARCH>,
|
||||
<0xb4 KEY_VOLUMEDOWN>,
|
||||
<0xbe KEY_SEARCH>;
|
||||
};
|
||||
|
||||
ir_key3 {
|
||||
rockchip,usercode = <0x1dcc>;
|
||||
rockchip,key_table =
|
||||
<0xee KEY_REPLY>,
|
||||
<0xf0 KEY_BACK>,
|
||||
<0xf8 KEY_UP>,
|
||||
<0xbb KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xed KEY_RIGHT>,
|
||||
<0xfc KEY_HOME>,
|
||||
<0xf1 KEY_VOLUMEUP>,
|
||||
<0xfd KEY_VOLUMEDOWN>,
|
||||
<0xb7 KEY_SEARCH>,
|
||||
<0xff KEY_POWER>,
|
||||
<0xf3 KEY_MUTE>,
|
||||
<0xbf KEY_MENU>,
|
||||
<0xf9 0x191>,
|
||||
<0xf5 0x192>,
|
||||
<0xb3 388>,
|
||||
<0xbe KEY_1>,
|
||||
<0xba KEY_2>,
|
||||
<0xb2 KEY_3>,
|
||||
<0xbd KEY_4>,
|
||||
<0xf9 KEY_5>,
|
||||
<0xb1 KEY_6>,
|
||||
<0xfc KEY_7>,
|
||||
<0xf8 KEY_8>,
|
||||
<0xb0 KEY_9>,
|
||||
<0xb6 KEY_0>,
|
||||
<0xb5 KEY_BACKSPACE>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vcc3v3_lcd_n {
|
||||
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
headphone {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd {
|
||||
lcd_rst_gpio: lcd-rst-gpio {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd {
|
||||
vcc_sd_h: vcc-sd-h {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
usb_host_pwren: usb-host-pwren {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usbc0_int: usbc0-int {
|
||||
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart1_gpios: uart1-gpios {
|
||||
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sai0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_lrck
|
||||
&i2s0m0_sclk
|
||||
&i2s0m0_sdi0
|
||||
&i2s0m0_sdo0>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
no-sd;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_host {
|
||||
status = "okay";
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
};
|
||||
|
||||
&u2phy_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
status = "okay";
|
||||
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
phys = <&u2phy_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,usb2-lpm-disable;
|
||||
usb-role-switch;
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dwc3_role_switch: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&usbc0_role_sw>;
|
||||
};
|
||||
};
|
||||
};
|
||||
325
arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi
Normal file
325
arch/arm64/boot/dts/rockchip/rk3562-evb2-cam.dtsi
Normal file
@@ -0,0 +1,325 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
vcc_mipicsi0: vcc-mipicsi0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mipicsi0_pwr>;
|
||||
regulator-name = "vcc_mipicsi0";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_mipicsi1: vcc-mipicsi1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mipicsi1_pwr>;
|
||||
regulator-name = "vcc_mipicsi1";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&gc8034_out0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy3 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&gc8034_out1>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy3_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi2_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
dw9714: dw9714@c {
|
||||
compatible = "dongwoon,dw9714";
|
||||
status = "okay";
|
||||
reg = <0x0c>;
|
||||
rockchip,vcm-start-current = <10>;
|
||||
rockchip,vcm-rated-current = <85>;
|
||||
rockchip,vcm-step-mode = <5>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
};
|
||||
|
||||
gc8034: gc8034@37 {
|
||||
compatible = "galaxycore,gc8034";
|
||||
reg = <0x37>;
|
||||
clocks = <&cru CLK_CAM0_OUT2IO>;
|
||||
clock-names = "xvclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camm0_clk0_out>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
// dvdd-supply = <&vcc_mipicsi0>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "RK-CMK-8M-2-v1";
|
||||
rockchip,camera-module-lens-name = "CK8401";
|
||||
lens-focus = <&dw9714>;
|
||||
port {
|
||||
gc8034_out0: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
dw9714_1: dw9714_1@c {
|
||||
compatible = "dongwoon,dw9714";
|
||||
status = "okay";
|
||||
reg = <0x0c>;
|
||||
rockchip,vcm-start-current = <10>;
|
||||
rockchip,vcm-rated-current = <85>;
|
||||
rockchip,vcm-step-mode = <5>;
|
||||
rockchip,camera-module-index = <1>;
|
||||
rockchip,camera-module-facing = "front";
|
||||
};
|
||||
|
||||
gc8034_1: gc8034_1@37 {
|
||||
compatible = "galaxycore,gc8034";
|
||||
reg = <0x37>;
|
||||
clocks = <&cru CLK_CAM2_OUT2IO>;
|
||||
clock-names = "xvclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cam_clk2_out>;
|
||||
reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
|
||||
// dvdd-supply = <&vcc_mipicsi1>;
|
||||
rockchip,camera-module-index = <1>;
|
||||
rockchip,camera-module-facing = "front";
|
||||
rockchip,camera-module-name = "RK-CMK-8M-2-v1";
|
||||
rockchip,camera-module-lens-name = "CK8401";
|
||||
lens-focus = <&dw9714_1>;
|
||||
port {
|
||||
gc8034_out1: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam1>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy1_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi2_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi2_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi2_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds2 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in1: endpoint {
|
||||
remote-endpoint = <&mipi2_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
mipi_lvds_sditf: endpoint {
|
||||
remote-endpoint = <&isp_vir0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds2_sditf {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
mipi_lvds2_sditf: endpoint {
|
||||
remote-endpoint = <&isp_vir1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_vir0 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp_vir0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi_lvds_sditf>;
|
||||
};
|
||||
isp_vir1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&mipi_lvds2_sditf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
mipicsi0_pwr: mipicsi0-pwr {
|
||||
rockchip,pins =
|
||||
/* camera power en */
|
||||
<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
mipicsi1_pwr: mipicsi1-pwr {
|
||||
rockchip,pins =
|
||||
/* camera1 power en */
|
||||
<3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb2-ddr4-v10.dtsi"
|
||||
#include "rk3562-linux.dtsi"
|
||||
#include "rk3562-rk809.dtsi"
|
||||
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb2-ddr4-v10.dts"
|
||||
|
||||
&pdm {
|
||||
/* The pin pdmm0_clk1 is conflict with i2s0_mclk which used by rk809_codec */
|
||||
pinctrl-0 = <&pdmm0_clk0
|
||||
&pdmm0_sdi0
|
||||
&pdmm0_sdi1
|
||||
&pdmm0_sdi2
|
||||
&pdmm0_sdi3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pdm_mic_array {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,112 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
#include "rk3562-evb2-ddr4-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk809.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB BT1120 TO HDMI V10 Ext Board";
|
||||
compatible = "rockchip,rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3562";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of gamc0 and bt1120 are multiplexed
|
||||
*/
|
||||
&gmac0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c1m1_xfer>;
|
||||
status = "okay";
|
||||
|
||||
sii9022: sii9022@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sii902x_hdmi_int>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
|
||||
enable-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
/*
|
||||
* MEDIA_BUS_FMT_YUYV8_1X16 for bt1120
|
||||
* MEDIA_BUS_FMT_UYVY8_2X8 for bt656
|
||||
*/
|
||||
bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
sii9022_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_sii9022>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
sii902x {
|
||||
sii902x_hdmi_int: sii902x-hdmi-int {
|
||||
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* <&bt1120_pins> for bt1120
|
||||
* <&bt656_pins> for bt656
|
||||
*/
|
||||
pinctrl-0 = <&bt1120_pins>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rgb_out_sii9022: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sii9022_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb_in_vp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rgb_in_vp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "okay";
|
||||
};
|
||||
10
arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts
Normal file
10
arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-evb2-ddr4-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk809.dtsi"
|
||||
#include "rk3562-evb2-cam.dtsi"
|
||||
522
arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi
Normal file
522
arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10.dtsi
Normal file
@@ -0,0 +1,522 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3562.dtsi"
|
||||
#include "rk3562-evb.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/sensor-dev.h>
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 EVB2 DDR4 V10 Board";
|
||||
compatible = "rockchip,rk3562-evb2-ddr4-v10", "rockchip,rk3562";
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
rk809_sound: rk809-sound {
|
||||
status = "okay";
|
||||
compatible = "rockchip,multicodecs-card";
|
||||
rockchip,card-name = "rockchip-rk809";
|
||||
hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
|
||||
rockchip,format = "i2s";
|
||||
rockchip,mclk-fs = <256>;
|
||||
rockchip,cpu = <&sai0>;
|
||||
rockchip,codec = <&rk809_codec>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_det>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
post-power-on-delay-ms = <200>;
|
||||
reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie20: vcc3v3-pcie20 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie20";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_host_pwren>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_pwren>;
|
||||
};
|
||||
|
||||
vcc3v3_clk: vcc3v3-clk {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_clk";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc25_ddr: vcc25-ddr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc25_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm6 0 5000 1>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
pwm-supply = <&vcc5v0_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
wifi_chip_type = "ap6275s";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
//wifi-bt-power-toggle;
|
||||
uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart1m0_rtsn>;
|
||||
pinctrl-1 = <&uart1_gpios>;
|
||||
BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy_pu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi_panel {
|
||||
power-supply = <&vcc3v3_lcd_n>;
|
||||
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_rst_gpio>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
tx_delay = <0x42>;
|
||||
/* rx_delay = <0x3f>; */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmiim0_miim
|
||||
&rgmiim0_tx_bus2
|
||||
&rgmiim0_rx_bus2
|
||||
&rgmiim0_rgmii_clk
|
||||
&rgmiim0_rgmii_bus
|
||||
ðm0_pins>;
|
||||
|
||||
phy-handle = <&rgmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
mpu6500_acc: mpu_acc@68 {
|
||||
compatible = "mpu6500_acc";
|
||||
reg = <0x68>;
|
||||
irq-gpio = <&gpio1 RK_PC7 IRQ_TYPE_EDGE_RISING>;
|
||||
irq_enable = <0>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_ACCEL>;
|
||||
layout = <3>;
|
||||
};
|
||||
|
||||
mpu6500_gyro: mpu_gyro@68 {
|
||||
compatible = "mpu6500_gyro";
|
||||
reg = <0x68>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_GYROSCOPE>;
|
||||
layout = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
|
||||
assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
headphone {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd {
|
||||
lcd_rst_gpio: lcd-rst-gpio {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
usb_host_pwren: usb-host-pwren {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_pwren: usb-otg-pwren {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart1_gpios: uart1-gpios {
|
||||
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
|
||||
compatible = "rockchip,remotectl-pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3m0_pins>;
|
||||
assigned-clocks = <&cru CLK_PMU1_PWM0>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
remote_pwm_id = <3>;
|
||||
handle_cpu_id = <1>;
|
||||
remote_support_psci = <1>;
|
||||
|
||||
ir_key1 {
|
||||
rockchip,usercode = <0x4040>;
|
||||
rockchip,key_table =
|
||||
<0xf2 KEY_REPLY>,
|
||||
<0xba KEY_BACK>,
|
||||
<0xf4 KEY_UP>,
|
||||
<0xf1 KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xee KEY_RIGHT>,
|
||||
<0xbd KEY_HOME>,
|
||||
<0xea KEY_VOLUMEUP>,
|
||||
<0xe3 KEY_VOLUMEDOWN>,
|
||||
<0xe2 KEY_SEARCH>,
|
||||
<0xb2 KEY_POWER>,
|
||||
<0xbc KEY_MUTE>,
|
||||
<0xec KEY_MENU>,
|
||||
<0xbf 0x190>,
|
||||
<0xe0 0x191>,
|
||||
<0xe1 0x192>,
|
||||
<0xe9 183>,
|
||||
<0xe6 248>,
|
||||
<0xe8 185>,
|
||||
<0xe7 186>,
|
||||
<0xf0 388>,
|
||||
<0xbe 0x175>;
|
||||
};
|
||||
|
||||
ir_key2 {
|
||||
rockchip,usercode = <0xff00>;
|
||||
rockchip,key_table =
|
||||
<0xf9 KEY_HOME>,
|
||||
<0xbf KEY_BACK>,
|
||||
<0xfb KEY_MENU>,
|
||||
<0xaa KEY_REPLY>,
|
||||
<0xb9 KEY_UP>,
|
||||
<0xe9 KEY_DOWN>,
|
||||
<0xb8 KEY_LEFT>,
|
||||
<0xea KEY_RIGHT>,
|
||||
<0xeb KEY_VOLUMEDOWN>,
|
||||
<0xef KEY_VOLUMEUP>,
|
||||
<0xf7 KEY_MUTE>,
|
||||
<0xe7 KEY_POWER>,
|
||||
<0xfc KEY_POWER>,
|
||||
<0xa9 KEY_VOLUMEDOWN>,
|
||||
<0xa8 KEY_VOLUMEDOWN>,
|
||||
<0xe0 KEY_VOLUMEDOWN>,
|
||||
<0xa5 KEY_VOLUMEDOWN>,
|
||||
<0xab 183>,
|
||||
<0xb7 388>,
|
||||
<0xe8 388>,
|
||||
<0xf8 184>,
|
||||
<0xaf 185>,
|
||||
<0xed KEY_VOLUMEDOWN>,
|
||||
<0xee 186>,
|
||||
<0xb3 KEY_VOLUMEDOWN>,
|
||||
<0xf1 KEY_VOLUMEDOWN>,
|
||||
<0xf2 KEY_VOLUMEDOWN>,
|
||||
<0xf3 KEY_SEARCH>,
|
||||
<0xb4 KEY_VOLUMEDOWN>,
|
||||
<0xbe KEY_SEARCH>;
|
||||
};
|
||||
|
||||
ir_key3 {
|
||||
rockchip,usercode = <0x1dcc>;
|
||||
rockchip,key_table =
|
||||
<0xee KEY_REPLY>,
|
||||
<0xf0 KEY_BACK>,
|
||||
<0xf8 KEY_UP>,
|
||||
<0xbb KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xed KEY_RIGHT>,
|
||||
<0xfc KEY_HOME>,
|
||||
<0xf1 KEY_VOLUMEUP>,
|
||||
<0xfd KEY_VOLUMEDOWN>,
|
||||
<0xb7 KEY_SEARCH>,
|
||||
<0xff KEY_POWER>,
|
||||
<0xf3 KEY_MUTE>,
|
||||
<0xbf KEY_MENU>,
|
||||
<0xf9 0x191>,
|
||||
<0xf5 0x192>,
|
||||
<0xb3 388>,
|
||||
<0xbe KEY_1>,
|
||||
<0xba KEY_2>,
|
||||
<0xb2 KEY_3>,
|
||||
<0xbd KEY_4>,
|
||||
<0xf9 KEY_5>,
|
||||
<0xb1 KEY_6>,
|
||||
<0xfc KEY_7>,
|
||||
<0xf8 KEY_8>,
|
||||
<0xb0 KEY_9>,
|
||||
<0xb6 KEY_0>,
|
||||
<0xb5 KEY_BACKSPACE>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_lrck
|
||||
&i2s0m0_sclk
|
||||
&i2s0m0_sdi0
|
||||
&i2s0m0_sdo0>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
no-sd;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif_8ch {
|
||||
pinctrl-0 = <&spdifm0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_host {
|
||||
status = "okay";
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
};
|
||||
|
||||
&u2phy_otg {
|
||||
status = "okay";
|
||||
vbus-supply = <&vcc5v0_usb_otg>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
extcon = <&u2phy>;
|
||||
maximum-speed = "high-speed";
|
||||
phys = <&u2phy_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,usb2-lpm-disable;
|
||||
};
|
||||
|
||||
&vcc3v3_lcd_n {
|
||||
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "okay";
|
||||
};
|
||||
23
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-dsm.dts
Normal file
23
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-dsm.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-iotest-lp3-v10.dts"
|
||||
|
||||
&dsm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsm_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
98
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts
Normal file
98
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts
Normal file
@@ -0,0 +1,98 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3562.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 IOTEST LP3 V10 Board";
|
||||
compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562";
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
dsm_sound: dsm-sound {
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,name = "rockchip,dsm-sound";
|
||||
simple-audio-card,bitclock-master = <&sndcodec>;
|
||||
simple-audio-card,frame-master = <&sndcodec>;
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&sai1>;
|
||||
};
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&dsm>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "rk3562-rk809.dtsi"
|
||||
|
||||
&combphy_pu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
extcon = <&u2phy>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,usb2-lpm-disable;
|
||||
};
|
||||
28
arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi
Normal file
28
arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi
Normal file
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen: chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
|
||||
};
|
||||
|
||||
fiq-debugger {
|
||||
compatible = "rockchip,fiq-debugger";
|
||||
rockchip,serial-id = <0>;
|
||||
rockchip,wake-irq = <0>;
|
||||
/* If enable uart uses irq instead of fiq */
|
||||
rockchip,irq-mode-enable = <1>;
|
||||
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
|
||||
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
2352
arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
Normal file
2352
arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
269
arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi
Normal file
269
arch/arm64/boot/dts/rockchip/rk3562-rk809.dtsi
Normal file
@@ -0,0 +1,269 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default", "pmic-sleep",
|
||||
"pmic-power-off", "pmic-reset";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
|
||||
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
|
||||
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
/* 1: rst regs (default in codes), 0: rst the pmic */
|
||||
pmic-reset-func = <0>;
|
||||
/* not save the PMIC_POWER_EN register in uboot */
|
||||
not-save-power-en = <1>;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl_rk8xx: pinctrl_rk8xx {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk817_slppin_null: rk817_slppin_null {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk817_slppin_slp: rk817_slppin_slp {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun1";
|
||||
};
|
||||
|
||||
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun2";
|
||||
};
|
||||
|
||||
rk817_slppin_rst: rk817_slppin_rst {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun3";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc2v8_dvp: LDO_REG1 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-name = "vcc2v8_dvp";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_dvp: LDO_REG9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rk809_codec: codec {
|
||||
#sound-dai-cells = <1>;
|
||||
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
|
||||
clocks = <&mclkout_sai0>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&mclkout_sai0>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_mclk>;
|
||||
hp-volume = <20>;
|
||||
spk-volume = <3>;
|
||||
mic-in-differential;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
307
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi
Normal file
307
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi
Normal file
@@ -0,0 +1,307 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
/ {
|
||||
vcc_mipipwr: vcc-mipipwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mipicam_pwr>;
|
||||
regulator-name = "vcc_mipipwr";
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&ov13855_out0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy4 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&gc8034_out0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy4_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi2_csi2_input>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4m0_xfer>;
|
||||
|
||||
dw9763: dw9763@c {
|
||||
compatible = "dongwoon,dw9763";
|
||||
status = "okay";
|
||||
reg = <0x0c>;
|
||||
rockchip,vcm-max-current = <120>;
|
||||
rockchip,vcm-start-current = <20>;
|
||||
rockchip,vcm-rated-current = <90>;
|
||||
rockchip,vcm-step-mode = <3>;
|
||||
rockchip,vcm-t-src = <0x20>;
|
||||
rockchip,vcm-t-div = <1>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
};
|
||||
|
||||
ov13855: ov13855@36 {
|
||||
status = "okay";
|
||||
compatible = "ovti,ov13855";
|
||||
reg = <0x36>;
|
||||
clocks = <&cru CLK_CAM0_OUT2IO>;
|
||||
clock-names = "xvclk";
|
||||
pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
avdd-supply = <&vcc2v8_dvp>;
|
||||
dovdd-supply = <&vcc_mipipwr>;
|
||||
dvdd-supply = <&vcc1v2_dvp>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "KYT-10203-v1";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
lens-focus = <&dw9763>;
|
||||
|
||||
port {
|
||||
ov13855_out0: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gc8034: gc8034@37 {
|
||||
compatible = "galaxycore,gc8034";
|
||||
status = "okay";
|
||||
reg = <0x37>;
|
||||
clocks = <&cru CLK_CAM0_OUT2IO>;
|
||||
clock-names = "xvclk";
|
||||
pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
avdd-supply = <&vcc2v8_dvp>;
|
||||
dovdd-supply = <&vcc_mipipwr>;
|
||||
dvdd-supply = <&vcc1v2_dvp>;
|
||||
rockchip,camera-module-index = <1>;
|
||||
rockchip,camera-module-facing = "front";
|
||||
rockchip,camera-module-name = "KYT-10203-v1";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
port {
|
||||
gc8034_out0: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam1>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy1_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy0_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi2_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi2_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy4_out>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi2_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in2>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camm0_clk0_out>;
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds2 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in2: endpoint {
|
||||
remote-endpoint = <&mipi2_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
mipi_lvds_sditf: endpoint {
|
||||
remote-endpoint = <&isp_vir0_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds2_sditf {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
mipi_lvds2_sditf: endpoint {
|
||||
remote-endpoint = <&isp_vir0_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_vir0 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp_vir0_in0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi_lvds_sditf>;
|
||||
};
|
||||
isp_vir0_in1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&mipi_lvds2_sditf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
mipicam_pwr: mipicam-pwr {
|
||||
rockchip,pins =
|
||||
/* camera power en */
|
||||
<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
1059
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
Normal file
1059
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
Normal file
File diff suppressed because it is too large
Load Diff
257
arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi
Normal file
257
arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi
Normal file
@@ -0,0 +1,257 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk817: pmic@20 {
|
||||
compatible = "rockchip,rk817";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default", "pmic-sleep",
|
||||
"pmic-power-off", "pmic-reset";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
|
||||
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
|
||||
pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
/* 1: rst regs (default in codes), 0: rst the pmic */
|
||||
pmic-reset-func = <0>;
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc5-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_sys>;
|
||||
vcc9-supply = <&dcdc_boost>;
|
||||
pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl_rk8xx: pinctrl_rk8xx {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk817_slppin_null: rk817_slppin_null {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk817_slppin_slp: rk817_slppin_slp {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun1";
|
||||
};
|
||||
|
||||
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun2";
|
||||
};
|
||||
|
||||
rk817_slppin_rst: rk817_slppin_rst {
|
||||
pins = "gpio_slp";
|
||||
function = "pin_fun3";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_dvp: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc2v8_dvp: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-name = "vcc2v8_dvp";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
dcdc_boost: BOOST {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <4700000>;
|
||||
regulator-max-microvolt = <5400000>;
|
||||
regulator-name = "boost";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
otg_switch: OTG_SWITCH {
|
||||
regulator-name = "otg_switch";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rk817_codec: codec {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "rockchip,rk817-codec";
|
||||
clocks = <&mclkout_sai0>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&mclkout_sai0>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_mclk>;
|
||||
hp-volume = <20>;
|
||||
spk-volume = <3>;
|
||||
mic-in-differential;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
9
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts
Normal file
9
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-test1-ddr3-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk809.dtsi"
|
||||
209
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi
Normal file
209
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi
Normal file
@@ -0,0 +1,209 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3562.dtsi"
|
||||
#include "rk3562-evb.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 TEST1 DDR3 V10 Board";
|
||||
compatible = "rockchip,rk3562-test1-ddr3-v10", "rockchip,rk3562";
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_host_pwren>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_pwren>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc25_ddr: vcc25-ddr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc25_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm6 0 5000 1>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
pwm-supply = <&vcc5v0_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy_pu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
tx_delay = <0x3f>;
|
||||
/* rx_delay = <0x3f>; */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmiim1_miim
|
||||
&rgmiim1_tx_bus2
|
||||
&rgmiim1_rx_bus2
|
||||
&rgmiim1_rgmii_clk
|
||||
&rgmiim1_rgmii_bus
|
||||
ðm1_pins>;
|
||||
|
||||
phy-handle = <&rgmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
|
||||
assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
usb_host_pwren: usb-host-pwren {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_pwren: usb-otg-pwren {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd &sdmmc1_det>;
|
||||
/* Should disable gmac0 and fix hardware if enabling sdmmc1 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_host {
|
||||
status = "okay";
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
};
|
||||
|
||||
&u2phy_otg {
|
||||
status = "okay";
|
||||
vbus-supply = <&vcc5v0_usb_otg>;
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
extcon = <&u2phy>;
|
||||
};
|
||||
9
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts
Normal file
9
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3562-test2-ddr4-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk809.dtsi"
|
||||
115
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi
Normal file
115
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi
Normal file
@@ -0,0 +1,115 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3562.dtsi"
|
||||
#include "rk3562-evb.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 TEST2 DDR4 V10 Board";
|
||||
compatible = "rockchip,rk3562-test2-ddr4-v10", "rockchip,rk3562";
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm6 0 5000 1>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
pwm-supply = <&vcc5v0_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmiim0_miim
|
||||
&rgmiim0_tx_bus2
|
||||
&rgmiim0_rx_bus2
|
||||
&rgmiim0_clk>;
|
||||
|
||||
phy-handle = <&rmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rmii_phy: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
extcon = <&u2phy>;
|
||||
maximum-speed = "high-speed";
|
||||
phys = <&u2phy_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,usb2-lpm-disable;
|
||||
};
|
||||
|
||||
2598
arch/arm64/boot/dts/rockchip/rk3562.dtsi
Normal file
2598
arch/arm64/boot/dts/rockchip/rk3562.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@@ -75,6 +75,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_8ch>;
|
||||
};
|
||||
|
||||
@@ -366,7 +366,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -265,7 +265,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -229,7 +229,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -558,7 +558,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -376,7 +376,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -482,7 +482,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -487,7 +487,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vccsys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
@@ -208,6 +208,7 @@
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ROCKCHIP,SPDIF";
|
||||
simple-audio-card,mclk-fs = <128>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif_8ch>;
|
||||
};
|
||||
@@ -1088,7 +1089,7 @@
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: tcs4525@1c {
|
||||
compatible = "tcs,tcs452x";
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
regulator-compatible = "fan53555-reg";
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user