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arm64: dts: rockchip: rk3562: Change clkin div to 4 for aclk vo

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The aclk vop should be equal or greater than the half of dlck vop,
the highest frequency of dclk may be 148.5MHz, the aclk vop is 396MHz,
so change the clkin div to 4.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ibc47f31b7d03530929fd537020c60a39708ccdcb
This commit is contained in:
Finley Xiao
2023-08-17 09:23:00 +08:00
committed by Tao Huang
parent 812a80b857
commit 0e7bc1d765
1 changed files with 1 additions and 1 deletions
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arch/arm64/boot/dts/rockchip/rk3562.dtsi
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@@ -368,7 +368,7 @@
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<4 0x00a000a4 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,