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clk: rockchip: Add supprot to limit input rate for fractional divider

Browse Source 
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.

Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-03-28 15:12:24 +08:00
committed by Tao Huang
parent 5b68eec983
commit 0ee785bb30
14 changed files with 141 additions and 89 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/clk/rockchip/clk-px30.c
View File

@@ -21,6 +21,7 @@
#include "clk.h"
#define PX30_GRF_SOC_STATUS0 0x480
#define PX30_FRAC_MAX_PRATE 600000000
enum px30_plls {
apll, dpll, cpll, npll, apll_b_h, apll_b_l,
@@ -421,7 +422,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(6), 0,
PX30_CLKGATE_CON(2), 3, GFLAGS,
&px30_dclk_vopb_fracmux),
&px30_dclk_vopb_fracmux, 0),
GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
@@ -430,7 +431,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(9), 0,
PX30_CLKGATE_CON(2), 7, GFLAGS,
&px30_dclk_vopl_fracmux),
&px30_dclk_vopl_fracmux, 0),
GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(2), 8, GFLAGS),
@@ -556,7 +557,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(27), 0,
PX30_CLKGATE_CON(9), 10, GFLAGS,
&px30_pdm_fracmux),
&px30_pdm_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(9), 11, GFLAGS),
@@ -566,7 +567,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(29), 0,
PX30_CLKGATE_CON(9), 13, GFLAGS,
&px30_i2s0_tx_fracmux),
&px30_i2s0_tx_fracmux, PX30_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
PX30_CLKGATE_CON(9), 14, GFLAGS),
@@ -582,7 +583,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(59), 0,
PX30_CLKGATE_CON(17), 1, GFLAGS,
&px30_i2s0_rx_fracmux),
&px30_i2s0_rx_fracmux, PX30_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
PX30_CLKGATE_CON(17), 2, GFLAGS),
@@ -598,7 +599,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(31), 0,
PX30_CLKGATE_CON(10), 1, GFLAGS,
&px30_i2s1_fracmux),
&px30_i2s1_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
@@ -613,7 +614,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(33), 0,
PX30_CLKGATE_CON(10), 5, GFLAGS,
&px30_i2s2_fracmux),
&px30_i2s2_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
@@ -631,7 +632,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(36), 0,
PX30_CLKGATE_CON(10), 14, GFLAGS,
&px30_uart1_fracmux),
&px30_uart1_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 15, GFLAGS),
@@ -644,7 +645,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(39), 0,
PX30_CLKGATE_CON(11), 2, GFLAGS,
&px30_uart2_fracmux),
&px30_uart2_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 3, GFLAGS),
@@ -657,7 +658,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(42), 0,
PX30_CLKGATE_CON(11), 6, GFLAGS,
&px30_uart3_fracmux),
&px30_uart3_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 7, GFLAGS),
@@ -670,7 +671,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(45), 0,
PX30_CLKGATE_CON(11), 10, GFLAGS,
&px30_uart4_fracmux),
&px30_uart4_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 11, GFLAGS),
@@ -683,7 +684,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(48), 0,
PX30_CLKGATE_CON(11), 14, GFLAGS,
&px30_uart5_fracmux),
&px30_uart5_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(11), 15, GFLAGS),
@@ -880,7 +881,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
PX30_PMU_CLKSEL_CON(1), 0,
PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
&px30_rtc32k_pmu_fracmux),
&px30_rtc32k_pmu_fracmux, 0),
COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
@@ -902,7 +903,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(5), 0,
PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
&px30_uart0_pmu_fracmux),
&px30_uart0_pmu_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),

13
drivers/clk/rockchip/clk-rk3036.c
View File

@@ -24,6 +24,9 @@
#include "clk.h"
#define RK3036_GRF_SOC_STATUS0 0x14c
#define RK3036_UART_FRAC_MAX_PRATE 600000000
#define RK3036_I2S_FRAC_MAX_PRATE 600000000
#define RK3036_SPDIF_FRAC_MAX_PRATE 600000000
enum rk3036_plls {
apll, dpll, gpll,
@@ -261,15 +264,15 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&rk3036_uart0_fracmux),
&rk3036_uart0_fracmux, RK3036_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&rk3036_uart1_fracmux),
&rk3036_uart1_fracmux, RK3036_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3036_uart2_fracmux),
&rk3036_uart2_fracmux, RK3036_UART_FRAC_MAX_PRATE),
COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
@@ -322,7 +325,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3036_i2s_fracmux),
&rk3036_i2s_fracmux, RK3036_I2S_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
RK2928_CLKGATE_CON(0), 13, GFLAGS),
@@ -335,7 +338,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3036_spdif_fracmux),
&rk3036_spdif_fracmux, RK3036_SPDIF_FRAC_MAX_PRATE),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),

15
drivers/clk/rockchip/clk-rk3128.c
View File

@@ -21,6 +21,9 @@
#include "clk.h"
#define RK3128_GRF_SOC_STATUS0 0x14c
#define RK3128_UART_FRAC_MAX_PRATE 600000000
#define RK3128_I2S_FRAC_MAX_PRATE 600000000
#define RK3128_SPDIF_FRAC_MAX_PRATE 600000000
enum rk3128_plls {
apll, dpll, cpll, gpll,
@@ -366,7 +369,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(8), 0,
RK2928_CLKGATE_CON(4), 5, GFLAGS,
&rk3128_i2s0_fracmux),
&rk3128_i2s0_fracmux, RK3128_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(4), 6, GFLAGS),
@@ -376,7 +379,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3128_i2s1_fracmux),
&rk3128_i2s1_fracmux, RK3128_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
@@ -389,7 +392,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3128_spdif_fracmux),
&rk3128_spdif_fracmux, RK3128_SPDIF_FRAC_MAX_PRATE),
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
@@ -426,15 +429,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&rk3128_uart0_fracmux),
&rk3128_uart0_fracmux, RK3128_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&rk3128_uart1_fracmux),
&rk3128_uart1_fracmux, RK3128_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3128_uart2_fracmux),
&rk3128_uart2_fracmux, RK3128_UART_FRAC_MAX_PRATE),
COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,

24
drivers/clk/rockchip/clk-rk3188.c
View File

@@ -22,6 +22,10 @@
#define RK3066_GRF_SOC_STATUS 0x15c
#define RK3188_GRF_SOC_STATUS 0xac
#define RK3188_UART_FRAC_MAX_PRATE 600000000
#define RK3188_I2S_FRAC_MAX_PRATE 600000000
#define RK3188_SPDIF_FRAC_MAX_PRATE 600000000
#define RK3188_HSADC_FRAC_MAX_PRATE 300000000
enum rk3188_plls {
apll, cpll, dpll, gpll,
@@ -371,7 +375,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
RK2928_CLKSEL_CON(23), 0,
RK2928_CLKGATE_CON(2), 7, GFLAGS,
&common_hsadc_out_fracmux),
&common_hsadc_out_fracmux, RK3188_HSADC_FRAC_MAX_PRATE),
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
RK2928_CLKSEL_CON(22), 7, IFLAGS),
@@ -385,7 +389,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(0), 14, GFLAGS,
&common_spdif_fracmux),
&common_spdif_fracmux, RK3188_SPDIF_FRAC_MAX_PRATE),
/*
* Clock-Architecture Diagram 4
@@ -419,28 +423,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&common_uart0_fracmux),
&common_uart0_fracmux, RK3188_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&common_uart1_fracmux),
&common_uart1_fracmux, RK3188_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&common_uart2_fracmux),
&common_uart2_fracmux, RK3188_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(1), 15, GFLAGS,
&common_uart3_fracmux),
&common_uart3_fracmux, RK3188_UART_FRAC_MAX_PRATE),
GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
@@ -626,21 +630,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
RK2928_CLKSEL_CON(6), 0,
RK2928_CLKGATE_CON(0), 8, GFLAGS,
&rk3066a_i2s0_fracmux),
&rk3066a_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3066a_i2s1_fracmux),
&rk3066a_i2s1_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
RK2928_CLKSEL_CON(8), 0,
RK2928_CLKGATE_CON(0), 12, GFLAGS,
&rk3066a_i2s2_fracmux),
&rk3066a_i2s2_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
@@ -734,7 +738,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3188_i2s0_fracmux),
&rk3188_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),

18
drivers/clk/rockchip/clk-rk3228.c
View File

@@ -23,6 +23,10 @@
#define RK3228_GRF_SOC_STATUS0 0x480
#define RK3228_UART_FRAC_MAX_PRATE 600000000
#define RK3228_SPDIF_FRAC_MAX_PRATE 600000000
#define RK3228_I2S_FRAC_MAX_PRATE 600000000
enum rk3228_plls {
apll, dpll, cpll, gpll,
};
@@ -402,7 +406,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(8), 0,
RK2928_CLKGATE_CON(0), 4, GFLAGS,
&rk3228_i2s0_fracmux),
&rk3228_i2s0_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
@@ -412,7 +416,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 11, GFLAGS,
&rk3228_i2s1_fracmux),
&rk3228_i2s1_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
@@ -425,7 +429,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(30), 0,
RK2928_CLKGATE_CON(0), 8, GFLAGS,
&rk3228_i2s2_fracmux),
&rk3228_i2s2_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
@@ -435,7 +439,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3228_spdif_fracmux),
&rk3228_spdif_fracmux, RK3228_SPDIF_FRAC_MAX_PRATE),
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
@@ -470,15 +474,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&rk3228_uart0_fracmux),
&rk3228_uart0_fracmux, RK3228_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&rk3228_uart1_fracmux),
&rk3228_uart1_fracmux, RK3228_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3228_uart2_fracmux),
&rk3228_uart2_fracmux, RK3228_UART_FRAC_MAX_PRATE),
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,

19
drivers/clk/rockchip/clk-rk3288.c
View File

@@ -22,6 +22,9 @@
#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
#define RK3288_GRF_SOC_STATUS1 0x284
#define RK3288_UART_FRAC_MAX_PRATE 600000000
#define RK3288_I2S_FRAC_MAX_PRATE 600000000
#define RK3288_SPDIF_FRAC_MAX_PRATE 600000000
enum rk3288_plls {
apll, dpll, cpll, gpll, npll,
@@ -348,7 +351,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(8), 0,
RK3288_CLKGATE_CON(4), 2, GFLAGS,
&rk3288_i2s_fracmux),
&rk3288_i2s_fracmux, RK3288_I2S_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
RK3288_CLKGATE_CON(4), 0, GFLAGS),
@@ -363,7 +366,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(9), 0,
RK3288_CLKGATE_CON(4), 5, GFLAGS,
&rk3288_spdif_fracmux),
&rk3288_spdif_fracmux, RK3288_SPDIF_FRAC_MAX_PRATE),
GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 6, GFLAGS),
COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
@@ -372,7 +375,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(41), 0,
RK3288_CLKGATE_CON(4), 8, GFLAGS,
&rk3288_spdif_8ch_fracmux),
&rk3288_spdif_8ch_fracmux, RK3288_SPDIF_FRAC_MAX_PRATE),
GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 9, GFLAGS),
@@ -573,7 +576,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(17), 0,
RK3288_CLKGATE_CON(1), 9, GFLAGS,
&rk3288_uart0_fracmux),
&rk3288_uart0_fracmux, RK3288_UART_FRAC_MAX_PRATE),
MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
@@ -582,28 +585,28 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(18), 0,
RK3288_CLKGATE_CON(1), 11, GFLAGS,
&rk3288_uart1_fracmux),
&rk3288_uart1_fracmux, RK3288_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(19), 0,
RK3288_CLKGATE_CON(1), 13, GFLAGS,
&rk3288_uart2_fracmux),
&rk3288_uart2_fracmux, RK3288_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(20), 0,
RK3288_CLKGATE_CON(1), 15, GFLAGS,
&rk3288_uart3_fracmux),
&rk3288_uart3_fracmux, RK3288_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(7), 0,
RK3288_CLKGATE_CON(2), 13, GFLAGS,
&rk3288_uart4_fracmux),
&rk3288_uart4_fracmux, RK3288_UART_FRAC_MAX_PRATE),
COMPOSITE(SCLK_MAC_PLL, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,

4
drivers/clk/rockchip/clk-rk3308.c
View File

@@ -466,6 +466,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux, 0),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RK3308_CLKGATE_CON(1), 8, GFLAGS),

17
drivers/clk/rockchip/clk-rk3328.c
View File

@@ -24,6 +24,9 @@
#define RK3328_GRF_SOC_STATUS0 0x480
#define RK3328_GRF_MAC_CON1 0x904
#define RK3328_GRF_MAC_CON2 0x908
#define RK3328_I2S_FRAC_MAX_PRATE 600000000
#define RK3328_UART_FRAC_MAX_PRATE 600000000
#define RK3328_SPDIF_FRAC_MAX_PRATE 600000000
enum rk3328_plls {
apll, dpll, cpll, gpll, npll,
@@ -380,7 +383,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(7), 0,
RK3328_CLKGATE_CON(1), 2, GFLAGS,
&rk3328_i2s0_fracmux),
&rk3328_i2s0_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 3, GFLAGS),
@@ -390,7 +393,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(9), 0,
RK3328_CLKGATE_CON(1), 5, GFLAGS,
&rk3328_i2s1_fracmux),
&rk3328_i2s1_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
@@ -403,7 +406,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(11), 0,
RK3328_CLKGATE_CON(1), 9, GFLAGS,
&rk3328_i2s2_fracmux),
&rk3328_i2s2_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
@@ -416,7 +419,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(13), 0,
RK3328_CLKGATE_CON(1), 13, GFLAGS,
&rk3328_spdif_fracmux),
&rk3328_spdif_fracmux, RK3328_SPDIF_FRAC_MAX_PRATE),
/* PD_UART */
COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
@@ -431,15 +434,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(15), 0,
RK3328_CLKGATE_CON(1), 15, GFLAGS,
&rk3328_uart0_fracmux),
&rk3328_uart0_fracmux, RK3328_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(17), 0,
RK3328_CLKGATE_CON(2), 1, GFLAGS,
&rk3328_uart1_fracmux),
&rk3328_uart1_fracmux, RK3328_UART_FRAC_MAX_PRATE),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(19), 0,
RK3328_CLKGATE_CON(2), 3, GFLAGS,
&rk3328_uart2_fracmux),
&rk3328_uart2_fracmux, RK3328_UART_FRAC_MAX_PRATE),
/*
* Clock-Architecture Diagram 4

17
drivers/clk/rockchip/clk-rk3368.c
View File

@@ -20,6 +20,9 @@
#include "clk.h"
#define RK3368_GRF_SOC_STATUS0 0x480
#define RK3368_I2S_FRAC_MAX_PRATE 600000000
#define RK3368_UART_FRAC_MAX_PRATE 600000000
#define RK3368_SPDIF_FRAC_MAX_PRATE 600000000
enum rk3368_plls {
apllb, aplll, dpll, cpll, gpll, npll,
@@ -405,7 +408,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
&rk3368_i2s_8ch_fracmux),
&rk3368_i2s_8ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(6), 0, GFLAGS),
@@ -417,7 +420,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(32), 0,
RK3368_CLKGATE_CON(6), 5, GFLAGS,
&rk3368_spdif_8ch_fracmux),
&rk3368_spdif_8ch_fracmux, RK3368_SPDIF_FRAC_MAX_PRATE),
GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
@@ -426,7 +429,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(54), 0,
RK3368_CLKGATE_CON(5), 14, GFLAGS,
&rk3368_i2s_2ch_fracmux),
&rk3368_i2s_2ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(5), 15, GFLAGS),
@@ -627,7 +630,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(34), 0,
RK3368_CLKGATE_CON(2), 1, GFLAGS,
&rk3368_uart0_fracmux),
&rk3368_uart0_fracmux, RK3368_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
@@ -635,7 +638,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(36), 0,
RK3368_CLKGATE_CON(2), 3, GFLAGS,
&rk3368_uart1_fracmux),
&rk3368_uart1_fracmux, RK3368_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
@@ -643,7 +646,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(40), 0,
RK3368_CLKGATE_CON(2), 7, GFLAGS,
&rk3368_uart3_fracmux),
&rk3368_uart3_fracmux, RK3368_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
@@ -651,7 +654,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(42), 0,
RK3368_CLKGATE_CON(2), 9, GFLAGS,
&rk3368_uart4_fracmux),
&rk3368_uart4_fracmux, RK3368_UART_FRAC_MAX_PRATE),
COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,

32
drivers/clk/rockchip/clk-rk3399.c
View File

@@ -21,6 +21,12 @@
#include <dt-bindings/clock/rk3399-cru.h>
#include "clk.h"
#define RK3399_I2S_FRAC_MAX_PRATE 600000000
#define RK3399_UART_FRAC_MAX_PRATE 600000000
#define RK3399_SPDIF_FRAC_MAX_PRATE 600000000
#define RK3399_VOP_FRAC_MAX_PRATE 600000000
#define RK3399_WIFI_FRAC_MAX_PRATE 600000000
enum rk3399_plls {
lpll, bpll, dpll, cpll, gpll, npll, vpll,
};
@@ -676,7 +682,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
RK3399_CLKSEL_CON(99), 0,
RK3399_CLKGATE_CON(8), 14, GFLAGS,
&rk3399_spdif_fracmux),
&rk3399_spdif_fracmux, RK3399_SPDIF_FRAC_MAX_PRATE),
GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 15, GFLAGS),
@@ -690,7 +696,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
RK3399_CLKSEL_CON(96), 0,
RK3399_CLKGATE_CON(8), 4, GFLAGS,
&rk3399_i2s0_fracmux),
&rk3399_i2s0_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 5, GFLAGS),
@@ -700,7 +706,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
RK3399_CLKSEL_CON(97), 0,
RK3399_CLKGATE_CON(8), 7, GFLAGS,
&rk3399_i2s1_fracmux),
&rk3399_i2s1_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 8, GFLAGS),
@@ -710,7 +716,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
RK3399_CLKSEL_CON(98), 0,
RK3399_CLKGATE_CON(8), 10, GFLAGS,
&rk3399_i2s2_fracmux),
&rk3399_i2s2_fracmux, RK3399_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 11, GFLAGS),
@@ -729,7 +735,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
RK3399_CLKSEL_CON(100), 0,
RK3399_CLKGATE_CON(9), 1, GFLAGS,
&rk3399_uart0_fracmux),
&rk3399_uart0_fracmux, RK3399_UART_FRAC_MAX_PRATE),
MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
@@ -739,7 +745,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
RK3399_CLKSEL_CON(101), 0,
RK3399_CLKGATE_CON(9), 3, GFLAGS,
&rk3399_uart1_fracmux),
&rk3399_uart1_fracmux, RK3399_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
@@ -747,7 +753,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
RK3399_CLKSEL_CON(102), 0,
RK3399_CLKGATE_CON(9), 5, GFLAGS,
&rk3399_uart2_fracmux),
&rk3399_uart2_fracmux, RK3399_UART_FRAC_MAX_PRATE),
COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
@@ -755,7 +761,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
RK3399_CLKSEL_CON(103), 0,
RK3399_CLKGATE_CON(9), 7, GFLAGS,
&rk3399_uart3_fracmux),
&rk3399_uart3_fracmux, RK3399_UART_FRAC_MAX_PRATE),
COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
@@ -1265,7 +1271,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
/* The VOP0 is main screen, it is able to re-set parent rate. */
COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(106), 0,
&rk3399_dclk_vop0_fracmux),
&rk3399_dclk_vop0_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -1302,7 +1308,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
RK3399_CLKSEL_CON(107), 0,
&rk3399_dclk_vop1_fracmux),
&rk3399_dclk_vop1_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
@@ -1416,7 +1422,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
RK3399_CLKSEL_CON(105), 0,
RK3399_CLKGATE_CON(13), 9, GFLAGS),
RK3399_CLKGATE_CON(13), 9, GFLAGS, 0),
DIV(0, "clk_test_24m", "xin24m", 0,
RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
@@ -1521,7 +1527,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
RK3399_PMU_CLKSEL_CON(7), 0,
&rk3399_pmuclk_wifi_fracmux),
&rk3399_pmuclk_wifi_fracmux, RK3399_WIFI_FRAC_MAX_PRATE),
MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
@@ -1553,7 +1559,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
RK3399_PMU_CLKSEL_CON(6), 0,
RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
&rk3399_uart4_pmu_fracmux),
&rk3399_uart4_pmu_fracmux, RK3399_UART_FRAC_MAX_PRATE),
DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),

14
drivers/clk/rockchip/clk-rv1108.c
View File

@@ -22,6 +22,8 @@
#include "clk.h"
#define RV1108_GRF_SOC_STATUS0 0x480
#define RV1108_I2S_FRAC_MAX_RATE 600000000
#define RV1108_UART_FRAC_MAX_RATE 600000000
enum rv1108_plls {
apll, dpll, gpll,
@@ -512,7 +514,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(8), 0,
RV1108_CLKGATE_CON(2), 1, GFLAGS,
&rv1108_i2s0_fracmux),
&rv1108_i2s0_fracmux, RV1108_I2S_FRAC_MAX_RATE),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
@@ -525,7 +527,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(2), 5, GFLAGS,
&rv1108_i2s1_fracmux),
&rv1108_i2s1_fracmux, RV1108_I2S_FRAC_MAX_RATE),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 6, GFLAGS),
@@ -535,7 +537,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(10), 0,
RV1108_CLKGATE_CON(2), 9, GFLAGS,
&rv1108_i2s2_fracmux),
&rv1108_i2s2_fracmux, RV1108_I2S_FRAC_MAX_RATE),
GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RV1108_CLKGATE_CON(2), 10, GFLAGS),
@@ -601,15 +603,15 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(16), 0,
RV1108_CLKGATE_CON(3), 2, GFLAGS,
&rv1108_uart0_fracmux),
&rv1108_uart0_fracmux, RV1108_UART_FRAC_MAX_RATE),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(17), 0,
RV1108_CLKGATE_CON(3), 4, GFLAGS,
&rv1108_uart1_fracmux),
&rv1108_uart1_fracmux, RV1108_UART_FRAC_MAX_RATE),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RV1108_CLKSEL_CON(18), 0,
RV1108_CLKGATE_CON(3), 6, GFLAGS,
&rv1108_uart2_fracmux),
&rv1108_uart2_fracmux, RV1108_UART_FRAC_MAX_RATE),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
RV1108_CLKGATE_CON(13), 10, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,

16
drivers/clk/rockchip/clk.c
View File

@@ -189,15 +189,24 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
unsigned long p_rate, p_parent_rate;
struct clk_hw *p_parent;
unsigned long scale;
u32 div;
p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
p_parent_rate = clk_hw_get_rate(p_parent);
*parent_rate = p_parent_rate;
if (fd->max_prate && p_parent_rate > fd->max_prate) {
div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
*parent_rate = p_parent_rate / div;
}
if (*parent_rate < rate * 20) {
pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
clk_hw_get_name(hw), *parent_rate, rate);
*m = 0;
*n = 1;
return;
}
}
@@ -222,7 +231,7 @@ static struct clk *rockchip_clk_register_frac_branch(
void __iomem *base, int muxdiv_offset, u8 div_flags,
int gate_offset, u8 gate_shift, u8 gate_flags,
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
unsigned long max_prate, spinlock_t *lock)
{
struct rockchip_clk_frac *frac;
struct clk *clk;
@@ -263,6 +272,7 @@ static struct clk *rockchip_clk_register_frac_branch(
div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
div->lock = lock;
div->approximation = rockchip_fractional_approximation;
div->max_prate = max_prate;
div_ops = &clk_fractional_divider_ops;
clk = clk_register_composite(NULL, name, parent_names, num_parents,
@@ -495,7 +505,7 @@ void __init rockchip_clk_register_branches(
list->div_flags,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, list->child,
&ctx->lock);
list->max_prate, &ctx->lock);
break;
case branch_half_divider:
clk = rockchip_clk_register_halfdiv(list->name,

10
drivers/clk/rockchip/clk.h
View File

@@ -417,6 +417,7 @@ struct rockchip_clk_branch {
u8 gate_shift;
u8 gate_flags;
struct rockchip_clk_branch *child;
unsigned long max_prate;
};
#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
@@ -534,7 +535,7 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
{ \
.id = _id, \
.branch_type = branch_fraction_divider, \
@@ -549,9 +550,10 @@ struct rockchip_clk_branch {
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
.max_prate = prate, \
}
#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
{ \
.id = _id, \
.branch_type = branch_fraction_divider, \
@@ -567,9 +569,10 @@ struct rockchip_clk_branch {
.gate_shift = gs, \
.gate_flags = gf, \
.child = ch, \
.max_prate = prate, \
}
#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
{ \
.id = _id, \
.branch_type = branch_fraction_divider, \
@@ -583,6 +586,7 @@ struct rockchip_clk_branch {
.div_flags = df, \
.gate_offset = -1, \
.child = ch, \
.max_prate = prate, \
}
#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \

2
include/linux/clk-provider.h
View File

@@ -592,6 +592,7 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* @mwidth: width of the numerator bit field
* @nshift: shift to the denominator bit field
* @nwidth: width of the denominator bit field
* @max_parent: the maximum frequency of fractional divider parent clock
* @lock: register lock
*
* Clock with adjustable fractional divider affecting its output frequency.
@@ -606,6 +607,7 @@ struct clk_fractional_divider {
u8 nwidth;
u32 nmask;
u8 flags;
unsigned long max_prate;
void (*approximation)(struct clk_hw *hw,
unsigned long rate, unsigned long *parent_rate,
unsigned long *m, unsigned long *n);