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clk: rockchip: drop severity of 'invalid clk rate' message

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These are noisy during boot:
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] rockchip_mmc_get_phase: invalid clk rate
[    0.000000] rockchip_mmc_get_phase: invalid clk rate
[    0.000000] rockchip_mmc_get_phase: invalid clk rate
[    0.000000] rockchip_mmc_get_phase: invalid clk rate
[    0.000000] rockchip_mmc_get_phase: invalid clk rate
[    0.000000] rockchip_mmc_get_phase: invalid clk rate
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (phys).

Change-Id: I0a5ca5a1e0b6c6ba9038fa64635dc448bb5c612b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Tao Huang
2018-03-27 17:02:10 +08:00
parent 4a67123cc7
commit 5b68eec983
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-mmc-phase.c
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@@ -62,7 +62,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
/* See the comment for rockchip_mmc_set_phase below */
if (!rate) {
pr_err("%s: invalid clk rate\n", __func__);
printk(KERN_DEBUG "%s: invalid clk rate\n", __func__);
return -EINVAL;
}