shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rk3228: Fix sclk_wifi div_width

Browse Source 
Change-Id: I8e216249fbd588ce55660eba9911fc59aedc920d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-03-18 21:41:43 +08:00
committed by Tao Huang
parent 0a3b4eb464
commit 4a67123cc7
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/rockchip/clk-rk3228.c
View File

@@ -178,7 +178,7 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
RK2928_MODE_CON, 8, 8, 0, NULL),
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
RK2928_MODE_CON, 12, 9, 0, rk3228_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
@@ -361,7 +361,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,