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phy: rockchip: mipi csi2 dphy fixes error of clk0 enable

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enable too early may lead to mipi csi2 overflow

Change-Id: Ib4d1f59803b8dcfdea8ba219fe8dc9667db35428
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
This commit is contained in:
Zefa Chen
2025-02-27 15:50:15 +08:00
committed by Tao Huang
parent 58732189b1
commit 1064d12c6d
1 changed files with 14 additions and 5 deletions
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19
drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
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@@ -879,10 +879,13 @@ static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
write_csi2_dphy_reg_mask(hw, CSI2PHY_CLK_CONTINUE_MODE,
0x30, CSI2PHY_CLK_CONTINUE_MODE_MASK);
} else {
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)) &&
hw->drv_data->chip_id < CHIP_ID_RK3588)
val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
if (dphy->phy_index % 3 == DPHY1) {
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
val |= (GENMASK(sensor->lanes - 1, 0) <<
CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
if (!(sensor->mbus.bus.mipi_csi2.flags &
@@ -1054,12 +1057,15 @@ static int csi2_dphy_hw_quick_stream_on(struct csi2_dphy *dphy,
CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
(0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
} else {
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)) &&
hw->drv_data->chip_id < CHIP_ID_RK3588)
val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
if (dphy->phy_index % 3 == DPHY1)
if (dphy->phy_index % 3 == DPHY1) {
val |= (GENMASK(sensor->lanes - 1, 0) <<
CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
}
if (dphy->phy_index % 3 == DPHY2) {
val |= (GENMASK(sensor->lanes - 1, 0) <<
@@ -1093,12 +1099,15 @@ static int csi2_dphy_hw_quick_stream_off(struct csi2_dphy *dphy,
CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
(0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
} else {
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)) &&
hw->drv_data->chip_id < CHIP_ID_RK3588)
val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
if (dphy->phy_index % 3 == DPHY1)
if (dphy->phy_index % 3 == DPHY1) {
val |= (GENMASK(sensor->lanes - 1, 0) <<
CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
}
if (dphy->phy_index % 3 == DPHY2) {
val |= (GENMASK(sensor->lanes - 1, 0) <<