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clk: rockchip: rk3588: Add CLK_SET_RATE_PARENT for i2s5/6 frac clk

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The flag was missing which makes i2s5/6 src clock rate can't be changed.

Change-Id: I3ad5f39e8a2826d0b18d554c3a53b55f219028d8
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This commit is contained in:
Joseph Chen
2022-09-07 15:46:08 +08:00
committed by Tao Huang
parent 3be39a0ab0
commit 11162a3487
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3588.c
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@@ -1996,7 +1996,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS,
RK3588_CLKGATE_CON(62), 6, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0,
COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(141), 0,
RK3588_CLKGATE_CON(62), 7, GFLAGS,
&rk3588_i2s5_8ch_tx_fracmux),
@@ -2014,7 +2014,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 0, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0,
COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(147), 0,
RK3588_CLKGATE_CON(63), 1, GFLAGS,
&rk3588_i2s6_8ch_rx_fracmux),