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phy: rockchip: naneng-combophy: Add pcie ext clk support

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Modify the dts for the combophy:
1. assign clock to 100MHz
2. add "rockchip,ext-refclk"

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I72c125ac6aa42dcf00761f32e20b10042fd9985d
This commit is contained in:
Kever Yang
2022-05-13 17:08:37 +08:00
committed by Tao Huang
parent be0c00efdc
commit 13ddb9150c
1 changed files with 21 additions and 0 deletions
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21
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -809,6 +809,27 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
return -EINVAL;
}
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
val = 0x10;
writel(val, priv->mmio + (0x20 << 2));
val = 0x0c;
writel(val, priv->mmio + (0x1b << 2));
/* Set up su_trim: */
val = 0xf0;
writel(val, priv->mmio + (0xa << 2));
val = 0x45;
writel(val, priv->mmio + (0xb << 2));
val = 0xb8;
writel(val, priv->mmio + (0xc << 2));
val = 0x59;
writel(val, priv->mmio + (0xd << 2));
}
}
return 0;
}