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ASoC: rk3308_codec: enable cut-off 20Hz high pass filter

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Change-Id: Ib97a8ee85ae7f4613a51e89da65503d18fa1de0b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2018-05-22 16:02:20 +08:00
committed by Tao Huang
parent 763b2b0fab
commit 14fbb1da27
2 changed files with 25 additions and 1 deletions
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11
sound/soc/codecs/rk3308_codec.c
View File

@@ -633,6 +633,17 @@ static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai,
RK3308_ADC_DIG_WORK,
RK3308_ADC_DIG_WORK);
/* Enable high pass filter and cut-off 20Hz for ADCs */
for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) {
regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(grp),
RK3308_ADC_HPF_PATH_MSK,
RK3308_ADC_HPF_PATH_EN);
udelay(10);
regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(grp),
RK3308_ADC_HPF_CUTOFF_MSK,
RK3308_ADC_HPF_CUTOFF_20HZ);
}
regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01,
RK3308_DAC_I2S_LRC_POL_MSK |
RK3308_DAC_I2S_MODE_MSK,

15
sound/soc/codecs/rk3308_codec.h
View File

@@ -26,7 +26,8 @@
#define ACODEC_ADC_I2S_CTL0 0x04 /* REG 0x01 */
#define ACODEC_ADC_I2S_CTL1 0x08 /* REG 0x02 */
#define ACODEC_ADC_BIST_MODE_SEL 0x0c /* REG 0x03 */
/* Resevred REG 0x04 ~ 0x06 */
#define ACODEC_ADC_HPF_PATH 0x10 /* REG 0x04 */
/* Resevred REG 0x05 ~ 0x06 */
#define ACODEC_ADC_DATA_PATH 0x1c /* REG 0x07 */
/* Resevred REG 0x08 ~ 0x0f */
@@ -123,6 +124,7 @@
#define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0)
#define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1)
#define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL)
#define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH)
#define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH)
#define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0)
@@ -273,6 +275,17 @@
#define RK3308_ADC_R_CH_BIST_CUBE (0x1 << RK3308_ADC_R_CH_BIST_SFT)
#define RK3308_ADC_R_CH_NORMAL_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */
/* RK3308_ADC_DIG_CON04 - REG: 0x0010 */
#define RK3308_ADC_HPF_PATH_SFT 2
#define RK3308_ADC_HPF_PATH_MSK (1 << RK3308_ADC_HPF_PATH_SFT)
#define RK3308_ADC_HPF_PATH_DIS (1 << RK3308_ADC_HPF_PATH_SFT)
#define RK3308_ADC_HPF_PATH_EN (0 << RK3308_ADC_HPF_PATH_SFT)
#define RK3308_ADC_HPF_CUTOFF_SFT 0
#define RK3308_ADC_HPF_CUTOFF_MSK (0x3 << RK3308_ADC_HPF_CUTOFF_SFT)
#define RK3308_ADC_HPF_CUTOFF_612HZ (0x2 << RK3308_ADC_HPF_CUTOFF_SFT)
#define RK3308_ADC_HPF_CUTOFF_245HZ (0x1 << RK3308_ADC_HPF_CUTOFF_SFT)
#define RK3308_ADC_HPF_CUTOFF_20HZ (0x0 << RK3308_ADC_HPF_CUTOFF_SFT)
/* RK3308_ADC_DIG_CON07 - REG: 0x001c */
#define RK3308_ADCL_DATA_SFT 4
#define RK3308_ADCL_DATA(x) (x << RK3308_ADCL_DATA_SFT)