shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: pll: fix up rk3588 pll setting

Browse Source 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ibf78a3c9d141da2bbb17026096aadbe26ddfd293
This commit is contained in:
Elaine Zhang
2021-11-15 17:43:59 +08:00
committed by Tao Huang
parent dbf2588e39
commit 150255a2ec
1 changed files with 2 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/rockchip/clk-pll.c
View File

@@ -1370,9 +1370,8 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
RK3588_PLLCON1_S_SHIFT),
pll->reg_base + RK3399_PLLCON(1));
if (rate->k)
writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK,
RK3588_PLLCON2_K_SHIFT),
writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK,
RK3588_PLLCON2_K_SHIFT),
pll->reg_base + RK3399_PLLCON(2));
/* set pll power up */