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arm64: dts: rockchip: rk3568: Fix PCIe30x2 DBI and remove useless clks

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Change-Id: Icae9ef5661b62abc588b3b86ddbd671772d5d5d5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2020-11-11 10:56:21 +08:00
parent 8a65d18577
commit 1603e4ecf6
1 changed files with 8 additions and 20 deletions
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28
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -1449,13 +1449,9 @@
#size-cells = <2>;
bus-range = <0x0 0x1f>;
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
<&cru CLK_PCIE20_AUX_NDFT>, <&cru CLK_PCIE20_AUX_DFT>,
<&cru CLK_PCIE20_PIPE_DFT>;
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux_ndft", "aux_dft",
"pipe_dft";
"aclk_dbi", "pclk";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
@@ -1473,7 +1469,7 @@
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x00000800 0x3 0x00000000 0x3 0x00000000 0x0 0x800000
0x81000000 0x3 0x00800000 0x3 0x00800000 0x0 0x100000
0x83000000 0x3 0x00900000 0x3 0x00900000 0x3 0x3f700000>;
0x83000000 0x3 0x00900000 0x3 0x00900000 0x0 0x3f700000>;
reg = <0x3 0xc0000000 0x0 0x400000>,
<0x0 0xfe260000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
@@ -1488,13 +1484,9 @@
#size-cells = <2>;
bus-range = <0x0 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>, <&cru CLK_PCIE30X1_AUX_DFT>,
<&cru CLK_PCIE30X1_PIPE_DFT>;
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux_ndft", "aux_dft",
"pipe_dft";
"aclk_dbi", "pclk";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
@@ -1528,13 +1520,9 @@
#size-cells = <2>;
bus-range = <0x0 0x1f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>, <&cru CLK_PCIE30X2_AUX_DFT>,
<&cru CLK_PCIE30X2_PIPE_DFT>;
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux_ndft", "aux_dft",
"pipe_dft";
"aclk_dbi", "pclk";
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
@@ -1553,7 +1541,7 @@
ranges = <0x00000800 0x3 0x80000000 0x3 0x80000000 0x0 0x800000
0x81000000 0x3 0x80800000 0x3 0x80800000 0x0 0x100000
0x83000000 0x3 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
reg = <0x3 0xc0400000 0x0 0x400000>,
reg = <0x3 0xc0800000 0x0 0x400000>,
<0x0 0xfe280000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_P_PCIE30X1>;