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phy: rockchip-samsung-hdptx-hdmi: Get actual frequency each time when enable dclk

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When HDMI0/1 are bound to the same VP, vop will only set one dclk rate,
The frequency of another dclk will not be changed. But HDMI driver will
set phy output frequency, The dclk core->rate does not correspond to the
actual phy output frequency. So dclk core->rate need to be updated when
enable dclk.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I497bf9a01b8210c17b1c720839fc8f5d15dd0baf
This commit is contained in:
Algea Cao
2022-03-18 09:20:22 +08:00
committed by Tao Huang
parent 504bc07b5b
commit 16776f1ef1
1 changed files with 2 additions and 1 deletions
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3
drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
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@@ -2070,6 +2070,7 @@ static int hdptx_phy_clk_enable(struct clk_hw *hw)
}
}
clk_get_rate(hdptx->dclk);
hdptx->count++;
return 0;
@@ -2117,7 +2118,7 @@ static int rockchip_hdptx_phy_clk_register(struct rockchip_hdptx_phy *hdptx)
init.parent_names = &parent_name;
init.num_parents = 1;
init.flags = 0;
init.flags = CLK_GET_RATE_NOCACHE;
if (!hdptx->id)
init.name = "clk_hdmiphy_pixel0";
else