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phy: rockchip: naneng-combphy: Adjust 100M refclk parameter for PCIe

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Change-Id: I94321c0b6bb64cff279b79c44b54f273ee52c897
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2021-02-06 09:20:18 +08:00
committed by Tao Huang
parent 34760af996
commit 179638095d
1 changed files with 9 additions and 12 deletions
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21
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -500,26 +500,23 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
case 100000000:
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_PCIE) {
/* PLL KVCO tuning fine */
val = readl(priv->mmio + (0x20 << 2));
val &= ~(0x7 << 2);
val |= 0x2 << 2;
writel(val, priv->mmio + (0x20 << 2));
/* Enable controlling random jitter, aka RMJ */
val = readl(priv->mmio + (0xb << 2));
val &= ~(0x7);
val |= 0x1 << 6 | 0x6;
writel(val, priv->mmio + (0xb << 2));
writel(0x4, priv->mmio + (0xb << 2));
val = readl(priv->mmio + (0x5 << 2));
val &= ~(0x3 << 6);
val |= 0x1 << 6;
writel(val, priv->mmio + (0x5 << 2));
val = readl(priv->mmio + (0x11 << 2));
val &= ~(0x7f);
val |= 0x19;
writel(val, priv->mmio + (0x11 << 2));
writel(0x32, priv->mmio + (0x11 << 2));
writel(0xf0, priv->mmio + (0xa << 2));
val = readl(priv->mmio + (0xa << 2));
val &= ~(0xf << 4);
val |= 0x7 << 4;
writel(val, priv->mmio + (0xa << 2));
}
break;
default: