mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-06 19:08:57 +09:00
Merge commit 'e74b58e2c6140fd37e40a0ac47bc9d1c7ddb219a'
* commit 'e74b58e2c6140fd37e40a0ac47bc9d1c7ddb219a': (81 commits) video: rockchip: rga3: add support for more Porter-Duff blend mode video: rockchip: rga3: remove old alpha config parameter video: rockchip: rga3: Modify the log printing of alpha config video: rockchip: rga3: remove the magic number in rga3 alpha config video: rockchip: rga3: remove the magic number in rga2 alpha config video: rockchip: rga3: print request_id and core_id when timeout video: rockchip: mpp: vepu2: fix multicore dispatch err ata: ahci: re-enabled FBS after issued software reset ARM: configs: rockchip_linux_defconfig: disable CONFIG_DM_VERITY media: rockchip: isp: no set clk if assigned-clock-rates in dts drm/rockchip: dsi2: Delete unused prop: USER_SPLIT_MODE drm/rockchip: dw_hdmi: Delete unused prop: USER_SPLIT_MODE drm/rockchip: vop2: rk3588 add support dual connector split mode drm/rockchip: drv: add split_area to identification left or right panel arm64: dts: rockchip: rk3399-evb: add WIFI,poweren_gpio for wifi mtd: spinand: gigadevice: Sync with upstream media: rockchip: isp: sync isp stream_on end then to start working arm64: dts: rockchip: rk3588-vehicle: fix gmac pinctrl-name error mtd: spinand: dosilicon: Modify redundant ECC status bits phy: rockchip: naneng-combphy: Fix swing from 250mV to 650mV for rk3562 pcie ... Signed-off-by: Tao Huang <huangtao@rock-chips.com> Conflicts: drivers/phy/rockchip/phy-rockchip-naneng-combphy.c drivers/soc/rockchip/rockchip_opp_select.c include/soc/rockchip/rockchip_opp_select.h sound/soc/rockchip/rockchip_i2s_tdm.c sound/soc/rockchip/rockchip_pdm.c Ignore: commited8ff84e98("soc: rockchip: opp_select: Implement rockchip_set_opp_supported_hw()"). commit2fe4992cb6("soc: rockchip: opp_select: Add support to parse 'rockchip,pvtm-voltage-sel-hw'"). Change-Id: I6d806db3fce856aae87d66572dd9823525614554 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
@@ -100,6 +100,15 @@ properties:
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description: Add this property to set the transmission method as CPU polling.
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type: boolean
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rockchip,cs-inactive-disable:
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description: Add this property to disable the cs inactive interrupt for spi
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slave.
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type: boolean
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ready-gpios:
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description: GPIO spec for the spi slave ready signal.
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maxItems: 1
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required:
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- compatible
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- reg
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@@ -168,7 +168,6 @@ CONFIG_MD=y
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CONFIG_BLK_DEV_DM=y
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CONFIG_DM_CRYPT=y
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CONFIG_DM_THIN_PROVISIONING=y
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CONFIG_DM_VERITY=y
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CONFIG_NETDEVICES=y
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CONFIG_TUN=y
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CONFIG_VETH=y
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@@ -414,11 +413,6 @@ CONFIG_DMADEVICES=y
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CONFIG_PL330_DMA=y
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CONFIG_STAGING=y
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CONFIG_ASHMEM=y
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CONFIG_FIQ_DEBUGGER=y
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CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
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CONFIG_FIQ_DEBUGGER_CONSOLE=y
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CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
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CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_ROCKCHIP_IOMMU=y
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CONFIG_CPU_RK312X=y
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@@ -437,6 +431,11 @@ CONFIG_ROCKCHIP_PVTM=y
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CONFIG_ROCKCHIP_SUSPEND_MODE=y
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CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
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CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y
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CONFIG_FIQ_DEBUGGER=y
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CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
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CONFIG_FIQ_DEBUGGER_CONSOLE=y
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CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
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CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
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CONFIG_PM_DEVFREQ=y
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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@@ -1,13 +1,117 @@
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CONFIG_ARM_PSCI=y
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CONFIG_CRYPTO=y
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# CONFIG_FIQ_DEBUGGER_FIQ_GLUE is not set
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CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
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CONFIG_TEE=y
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CONFIG_ARM_CPU_SUSPEND=y
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# CONFIG_ARM_CRYPTO is not set
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# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
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# CONFIG_ARM_PSCI_CPUIDLE is not set
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CONFIG_ARM_PSCI_FW=y
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# CONFIG_ARM_SCMI_PROTOCOL is not set
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CONFIG_ARM_SMCCC_SOC_ID=y
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# CONFIG_CRYPTO_842 is not set
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# CONFIG_CRYPTO_ADIANTUM is not set
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# CONFIG_CRYPTO_AEGIS128 is not set
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# CONFIG_CRYPTO_AES is not set
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# CONFIG_CRYPTO_AES_TI is not set
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CONFIG_CRYPTO_ALGAPI=y
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CONFIG_CRYPTO_ALGAPI2=y
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# CONFIG_CRYPTO_ANSI_CPRNG is not set
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# CONFIG_CRYPTO_AUTHENC is not set
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# CONFIG_CRYPTO_BLAKE2B is not set
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# CONFIG_CRYPTO_BLAKE2S is not set
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# CONFIG_CRYPTO_BLOWFISH is not set
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# CONFIG_CRYPTO_CAMELLIA is not set
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# CONFIG_CRYPTO_CAST5 is not set
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# CONFIG_CRYPTO_CAST6 is not set
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# CONFIG_CRYPTO_CBC is not set
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# CONFIG_CRYPTO_CCM is not set
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# CONFIG_CRYPTO_CFB is not set
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# CONFIG_CRYPTO_CHACHA20 is not set
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# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
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# CONFIG_CRYPTO_CMAC is not set
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# CONFIG_CRYPTO_CRC32 is not set
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# CONFIG_CRYPTO_CRC32C is not set
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# CONFIG_CRYPTO_CRCT10DIF is not set
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# CONFIG_CRYPTO_CRYPTD is not set
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# CONFIG_CRYPTO_CTR is not set
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# CONFIG_CRYPTO_CTS is not set
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# CONFIG_CRYPTO_CURVE25519 is not set
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# CONFIG_CRYPTO_DEFLATE is not set
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# CONFIG_CRYPTO_DES is not set
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# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
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# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
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# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
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# CONFIG_CRYPTO_DEV_CCREE is not set
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# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
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# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
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# CONFIG_CRYPTO_DH is not set
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# CONFIG_CRYPTO_DRBG_MENU is not set
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# CONFIG_CRYPTO_ECB is not set
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# CONFIG_CRYPTO_ECDH is not set
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# CONFIG_CRYPTO_ECHAINIV is not set
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# CONFIG_CRYPTO_ECRDSA is not set
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# CONFIG_CRYPTO_ESSIV is not set
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# CONFIG_CRYPTO_FCRYPT is not set
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# CONFIG_CRYPTO_GCM is not set
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# CONFIG_CRYPTO_GHASH is not set
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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# CONFIG_CRYPTO_HMAC is not set
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CONFIG_CRYPTO_HW=y
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# CONFIG_CRYPTO_JITTERENTROPY is not set
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# CONFIG_CRYPTO_KEYWRAP is not set
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# CONFIG_CRYPTO_LIB_CHACHA is not set
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# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
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# CONFIG_CRYPTO_LRW is not set
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# CONFIG_CRYPTO_LZ4 is not set
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# CONFIG_CRYPTO_LZ4HC is not set
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# CONFIG_CRYPTO_LZO is not set
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# CONFIG_CRYPTO_MANAGER is not set
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CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
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# CONFIG_CRYPTO_MD4 is not set
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# CONFIG_CRYPTO_MD5 is not set
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# CONFIG_CRYPTO_MICHAEL_MIC is not set
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# CONFIG_CRYPTO_NULL is not set
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# CONFIG_CRYPTO_OFB is not set
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# CONFIG_CRYPTO_PCBC is not set
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# CONFIG_CRYPTO_POLY1305 is not set
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# CONFIG_CRYPTO_RMD128 is not set
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# CONFIG_CRYPTO_RMD160 is not set
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# CONFIG_CRYPTO_RMD256 is not set
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# CONFIG_CRYPTO_RMD320 is not set
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# CONFIG_CRYPTO_RSA is not set
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# CONFIG_CRYPTO_SALSA20 is not set
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# CONFIG_CRYPTO_SEQIV is not set
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# CONFIG_CRYPTO_SERPENT is not set
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CONFIG_CRYPTO_SHA1=y
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# CONFIG_CRYPTO_SHA256 is not set
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# CONFIG_CRYPTO_SHA3 is not set
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# CONFIG_CRYPTO_SHA512 is not set
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# CONFIG_CRYPTO_SM2 is not set
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# CONFIG_CRYPTO_SM3 is not set
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# CONFIG_CRYPTO_SM4 is not set
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# CONFIG_CRYPTO_STREEBOG is not set
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# CONFIG_CRYPTO_TEST is not set
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# CONFIG_CRYPTO_TGR192 is not set
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# CONFIG_CRYPTO_TWOFISH is not set
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# CONFIG_CRYPTO_USER is not set
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# CONFIG_CRYPTO_USER_API_AEAD is not set
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# CONFIG_CRYPTO_USER_API_HASH is not set
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# CONFIG_CRYPTO_USER_API_RNG is not set
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# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
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# CONFIG_CRYPTO_VMAC is not set
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# CONFIG_CRYPTO_WP512 is not set
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# CONFIG_CRYPTO_XCBC is not set
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# CONFIG_CRYPTO_XTS is not set
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# CONFIG_CRYPTO_XXHASH is not set
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# CONFIG_CRYPTO_ZSTD is not set
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CONFIG_GLOB=y
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# CONFIG_GLOB_SELFTEST is not set
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CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
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CONFIG_HW_RANDOM_OPTEE=y
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CONFIG_LIB_MEMNEQ=y
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CONFIG_OPTEE=y
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CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
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CONFIG_SOC_BUS=y
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@@ -88,8 +88,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-spi-nand-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb
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@@ -103,6 +105,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb2lvds.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-k350c4516t.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-dual-camera.dtb
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@@ -161,6 +164,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb
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@@ -2696,27 +2696,27 @@
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i2s0 {
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i2s0_8ch_mclk: i2s0-8ch-mclk {
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rockchip,pins =
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<3 RK_PC1 2 &pcfg_pull_none>;
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<3 RK_PC1 2 &pcfg_pull_none_smt>;
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};
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i2s0_8ch_sclktx: i2s0-8ch-sclktx {
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rockchip,pins =
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<3 RK_PC3 2 &pcfg_pull_none>;
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<3 RK_PC3 2 &pcfg_pull_none_smt>;
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};
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i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
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rockchip,pins =
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<3 RK_PB4 2 &pcfg_pull_none>;
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<3 RK_PB4 2 &pcfg_pull_none_smt>;
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};
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i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
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rockchip,pins =
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<3 RK_PC2 2 &pcfg_pull_none>;
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<3 RK_PC2 2 &pcfg_pull_none_smt>;
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};
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i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
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rockchip,pins =
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<3 RK_PB5 2 &pcfg_pull_none>;
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<3 RK_PB5 2 &pcfg_pull_none_smt>;
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};
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i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
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@@ -2763,17 +2763,17 @@
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i2s1 {
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i2s1_2ch_mclk: i2s1-2ch-mclk {
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rockchip,pins =
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<2 RK_PC3 1 &pcfg_pull_none>;
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<2 RK_PC3 1 &pcfg_pull_none_smt>;
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};
|
||||
|
||||
i2s1_2ch_sclk: i2s1-2ch-sclk {
|
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rockchip,pins =
|
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<2 RK_PC2 1 &pcfg_pull_none>;
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<2 RK_PC2 1 &pcfg_pull_none_smt>;
|
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};
|
||||
|
||||
i2s1_2ch_lrck: i2s1-2ch-lrck {
|
||||
rockchip,pins =
|
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<2 RK_PC1 1 &pcfg_pull_none>;
|
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<2 RK_PC1 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s1_2ch_sdi: i2s1-2ch-sdi {
|
||||
@@ -2790,17 +2790,17 @@
|
||||
i2s2 {
|
||||
i2s2_2ch_mclk: i2s2-2ch-mclk {
|
||||
rockchip,pins =
|
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<3 RK_PA1 2 &pcfg_pull_none>;
|
||||
<3 RK_PA1 2 &pcfg_pull_none_smt>;
|
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};
|
||||
|
||||
i2s2_2ch_sclk: i2s2-2ch-sclk {
|
||||
rockchip,pins =
|
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<3 RK_PA2 2 &pcfg_pull_none>;
|
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<3 RK_PA2 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s2_2ch_lrck: i2s2-2ch-lrck {
|
||||
rockchip,pins =
|
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<3 RK_PA3 2 &pcfg_pull_none>;
|
||||
<3 RK_PA3 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s2_2ch_sdi: i2s2-2ch-sdi {
|
||||
|
||||
@@ -310,12 +310,12 @@
|
||||
dram_dll_dis_freq = <IGNORE_THIS>;
|
||||
phy_dll_dis_freq = <IGNORE_THIS>;
|
||||
/* drv when odt on */
|
||||
phy_dq_drv_odten = <35>;
|
||||
phy_dq_drv_odten = <44>;
|
||||
phy_ca_drv_odten = <38>;
|
||||
phy_clk_drv_odten = <47>;
|
||||
dram_dq_drv_odten = <40>;
|
||||
/* drv when odt off */
|
||||
phy_dq_drv_odtoff = <35>;
|
||||
phy_dq_drv_odtoff = <44>;
|
||||
phy_ca_drv_odtoff = <38>;
|
||||
phy_clk_drv_odtoff = <47>;
|
||||
dram_dq_drv_odtoff = <40>;
|
||||
@@ -328,11 +328,11 @@
|
||||
dram_dq_odt_en_freq = <800>;
|
||||
phy_odt_en_freq = <800>;
|
||||
/* slew rate when odt enable */
|
||||
phy_dq_sr_odten = <0x0>;
|
||||
phy_dq_sr_odten = <0x7>;
|
||||
phy_ca_sr_odten = <0x1>;
|
||||
phy_clk_sr_odten = <0x1>;
|
||||
/* slew rate when odt disable */
|
||||
phy_dq_sr_odtoff = <0x0>;
|
||||
phy_dq_sr_odtoff = <0x7>;
|
||||
phy_ca_sr_odtoff = <0x1>;
|
||||
phy_clk_sr_odtoff = <0x1>;
|
||||
/* ssmod setting*/
|
||||
@@ -371,7 +371,7 @@
|
||||
lp4_dq_vref_odten = <276>;
|
||||
lp4_ca_vref_odten = <380>;
|
||||
/* lp4 vref info when odt disable */
|
||||
phy_lp4_dq_vref_odtoff = <340>;
|
||||
phy_lp4_dq_vref_odtoff = <420>;
|
||||
lp4_dq_vref_odtoff = <420>;
|
||||
lp4_ca_vref_odtoff = <420>;
|
||||
};
|
||||
|
||||
@@ -2246,15 +2246,15 @@
|
||||
i2s1 {
|
||||
i2s1_2ch_lrck: i2s1-2ch-lrck {
|
||||
rockchip,pins =
|
||||
<3 RK_PA0 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PA0 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s1_2ch_sclk: i2s1-2ch-sclk {
|
||||
rockchip,pins =
|
||||
<3 RK_PA1 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PA1 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s1_2ch_mclk: i2s1-2ch-mclk {
|
||||
rockchip,pins =
|
||||
<3 RK_PA2 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PA2 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s1_2ch_sdo: i2s1-2ch-sdo {
|
||||
rockchip,pins =
|
||||
@@ -2281,11 +2281,11 @@
|
||||
};
|
||||
i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
|
||||
rockchip,pins =
|
||||
<3 RK_PB0 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PB0 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
|
||||
rockchip,pins =
|
||||
<3 RK_PB1 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PB1 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
|
||||
rockchip,pins =
|
||||
@@ -2301,15 +2301,15 @@
|
||||
};
|
||||
i2s0_8ch_mclk: i2s0-8ch-mclk {
|
||||
rockchip,pins =
|
||||
<3 RK_PB5 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PB5 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
|
||||
rockchip,pins =
|
||||
<3 RK_PB6 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PB6 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s0_8ch_sclktx: i2s0-8ch-sclktx {
|
||||
rockchip,pins =
|
||||
<3 RK_PB7 1 &pcfg_pull_none_2ma>;
|
||||
<3 RK_PB7 1 &pcfg_pull_none_2ma_smt>;
|
||||
};
|
||||
i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
|
||||
rockchip,pins =
|
||||
|
||||
@@ -1840,17 +1840,17 @@
|
||||
i2s_2ch_0 {
|
||||
i2s_2ch_0_mclk: i2s-2ch-0-mclk {
|
||||
rockchip,pins =
|
||||
<4 RK_PB4 1 &pcfg_pull_none>;
|
||||
<4 RK_PB4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_2ch_0_sclk: i2s-2ch-0-sclk {
|
||||
rockchip,pins =
|
||||
<4 RK_PB5 1 &pcfg_pull_none>;
|
||||
<4 RK_PB5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_2ch_0_lrck: i2s-2ch-0-lrck {
|
||||
rockchip,pins =
|
||||
<4 RK_PB6 1 &pcfg_pull_none>;
|
||||
<4 RK_PB6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_2ch_0_sdo: i2s-2ch-0-sdo {
|
||||
@@ -1867,27 +1867,27 @@
|
||||
i2s_8ch_0 {
|
||||
i2s_8ch_0_mclk: i2s-8ch-0-mclk {
|
||||
rockchip,pins =
|
||||
<2 RK_PA4 1 &pcfg_pull_none>;
|
||||
<2 RK_PA4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
|
||||
rockchip,pins =
|
||||
<2 RK_PA5 1 &pcfg_pull_none>;
|
||||
<2 RK_PA5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
|
||||
rockchip,pins =
|
||||
<2 RK_PA6 1 &pcfg_pull_none>;
|
||||
<2 RK_PA6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
|
||||
rockchip,pins =
|
||||
<2 RK_PA7 1 &pcfg_pull_none>;
|
||||
<2 RK_PA7 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
|
||||
rockchip,pins =
|
||||
<2 RK_PB0 1 &pcfg_pull_none>;
|
||||
<2 RK_PB0 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
|
||||
@@ -1934,27 +1934,27 @@
|
||||
i2s_8ch_1_m0 {
|
||||
i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
|
||||
rockchip,pins =
|
||||
<1 RK_PA2 2 &pcfg_pull_none>;
|
||||
<1 RK_PA2 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA3 2 &pcfg_pull_none>;
|
||||
<1 RK_PA3 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA4 2 &pcfg_pull_none>;
|
||||
<1 RK_PA4 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA5 2 &pcfg_pull_none>;
|
||||
<1 RK_PA5 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA6 2 &pcfg_pull_none>;
|
||||
<1 RK_PA6 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
|
||||
@@ -1986,27 +1986,27 @@
|
||||
i2s_8ch_1_m1 {
|
||||
i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
|
||||
rockchip,pins =
|
||||
<1 RK_PB4 2 &pcfg_pull_none>;
|
||||
<1 RK_PB4 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PB5 2 &pcfg_pull_none>;
|
||||
<1 RK_PB5 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PB6 2 &pcfg_pull_none>;
|
||||
<1 RK_PB6 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PB7 2 &pcfg_pull_none>;
|
||||
<1 RK_PB7 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PC0 2 &pcfg_pull_none>;
|
||||
<1 RK_PC0 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
|
||||
|
||||
@@ -9,6 +9,11 @@
|
||||
bias-disable;
|
||||
drive-strength-s = <4>;
|
||||
};
|
||||
pcfg_pull_none_0_4ma_smt: pcfg-pull-none-0-4ma-smt {
|
||||
bias-disable;
|
||||
drive-strength-s = <4>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
pcfg_pull_up_0_4ma: pcfg-pull-up-0-4ma {
|
||||
bias-pull-up;
|
||||
drive-strength-s = <4>;
|
||||
@@ -127,17 +132,17 @@
|
||||
i2s_2ch_0 {
|
||||
i2s_2ch_0_mclk: i2s-2ch-0-mclk {
|
||||
rockchip,pins =
|
||||
<4 RK_PB4 1 &pcfg_pull_none>;
|
||||
<4 RK_PB4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_2ch_0_sclk: i2s-2ch-0-sclk {
|
||||
rockchip,pins =
|
||||
<4 RK_PB5 1 &pcfg_pull_none>;
|
||||
<4 RK_PB5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
i2s_2ch_0_lrck: i2s-2ch-0-lrck {
|
||||
rockchip,pins =
|
||||
<4 RK_PB6 1 &pcfg_pull_none_0_4ma>;
|
||||
<4 RK_PB6 1 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_2ch_0_sdo: i2s-2ch-0-sdo {
|
||||
@@ -154,27 +159,27 @@
|
||||
i2s_8ch_0 {
|
||||
i2s_8ch_0_mclk: i2s-8ch-0-mclk {
|
||||
rockchip,pins =
|
||||
<2 RK_PA4 1 &pcfg_pull_none_0_4ma>;
|
||||
<2 RK_PA4 1 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
|
||||
rockchip,pins =
|
||||
<2 RK_PA5 1 &pcfg_pull_none_0_4ma>;
|
||||
<2 RK_PA5 1 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
|
||||
rockchip,pins =
|
||||
<2 RK_PA6 1 &pcfg_pull_none_0_4ma>;
|
||||
<2 RK_PA6 1 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
|
||||
rockchip,pins =
|
||||
<2 RK_PA7 1 &pcfg_pull_none_0_4ma>;
|
||||
<2 RK_PA7 1 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
|
||||
rockchip,pins =
|
||||
<2 RK_PB0 1 &pcfg_pull_none_0_4ma>;
|
||||
<2 RK_PB0 1 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
|
||||
@@ -222,27 +227,27 @@
|
||||
i2s_8ch_1_m0 {
|
||||
i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
|
||||
rockchip,pins =
|
||||
<1 RK_PA2 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PA2 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA3 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PA3 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA4 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PA4 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA5 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PA5 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PA6 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PA6 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
|
||||
@@ -274,27 +279,27 @@
|
||||
i2s_8ch_1_m1 {
|
||||
i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
|
||||
rockchip,pins =
|
||||
<1 RK_PB4 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PB4 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PB5 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PB5 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PB6 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PB6 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
|
||||
rockchip,pins =
|
||||
<1 RK_PB7 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PB7 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
|
||||
rockchip,pins =
|
||||
<1 RK_PC0 2 &pcfg_pull_none_0_4ma>;
|
||||
<1 RK_PC0 2 &pcfg_pull_none_0_4ma_smt>;
|
||||
};
|
||||
|
||||
i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
|
||||
|
||||
@@ -175,6 +175,7 @@
|
||||
wifi_chip_type = "ap6354";
|
||||
sdio_vref = <1800>;
|
||||
WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
|
||||
WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -210,6 +210,7 @@
|
||||
wifi_chip_type = "ap6354";
|
||||
sdio_vref = <1800>;
|
||||
WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
|
||||
WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -70,6 +70,7 @@
|
||||
wifi_chip_type = "ap6354";
|
||||
sdio_vref = <1800>;
|
||||
WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
|
||||
WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
14
arch/arm64/boot/dts/rockchip/rk3528-demo4-ddr4-v10-linux.dts
Normal file
14
arch/arm64/boot/dts/rockchip/rk3528-demo4-ddr4-v10-linux.dts
Normal file
@@ -0,0 +1,14 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3528-demo4-ddr4-v10.dtsi"
|
||||
#include "rk3528-linux.dtsi"
|
||||
|
||||
/ {
|
||||
chosen: chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
|
||||
};
|
||||
};
|
||||
@@ -7,6 +7,12 @@
|
||||
#include "rk3528-evb1-ddr4-v10.dtsi"
|
||||
#include "rk3528-linux.dtsi"
|
||||
|
||||
/ {
|
||||
chosen: chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3528-evb1-ddr4-v10.dtsi"
|
||||
#include "rk3528-linux.dtsi"
|
||||
|
||||
/ {
|
||||
chosen: chosen {
|
||||
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw rootwait";
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sfc {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
@@ -366,21 +366,21 @@
|
||||
i2s0m0_lrck: i2s0m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s0_lrck_m0 */
|
||||
<3 RK_PB6 1 &pcfg_pull_none>;
|
||||
<3 RK_PB6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m0_mclk: i2s0m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_mclk_m0 */
|
||||
<3 RK_PB4 1 &pcfg_pull_none>;
|
||||
<3 RK_PB4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m0_sclk: i2s0m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_sclk_m0 */
|
||||
<3 RK_PB5 1 &pcfg_pull_none>;
|
||||
<3 RK_PB5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -400,21 +400,21 @@
|
||||
i2s0m1_lrck: i2s0m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s0_lrck_m1 */
|
||||
<1 RK_PB6 1 &pcfg_pull_none>;
|
||||
<1 RK_PB6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m1_mclk: i2s0m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_mclk_m1 */
|
||||
<1 RK_PB4 1 &pcfg_pull_none>;
|
||||
<1 RK_PB4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m1_sclk: i2s0m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_sclk_m1 */
|
||||
<1 RK_PB5 1 &pcfg_pull_none>;
|
||||
<1 RK_PB5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -436,21 +436,21 @@
|
||||
i2s1_lrck: i2s1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s1_lrck */
|
||||
<4 RK_PA6 1 &pcfg_pull_none>;
|
||||
<4 RK_PA6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1_mclk: i2s1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1_mclk */
|
||||
<4 RK_PA4 1 &pcfg_pull_none>;
|
||||
<4 RK_PA4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1_sclk: i2s1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s1_sclk */
|
||||
<4 RK_PA5 1 &pcfg_pull_none>;
|
||||
<4 RK_PA5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
#include "rk3562-evb1-lp4x-v10.dtsi"
|
||||
#include "rk3562-android.dtsi"
|
||||
#include "rk3562-rk817.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SII9022 RGB2HDMI DISPLAY Ext Board";
|
||||
compatible = "rockchip,rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi", "rockchip,rk3562";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi_in_vp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of gmac0 and rgb are multiplexed
|
||||
*/
|
||||
&gmac0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c3m0_xfer>;
|
||||
status = "okay";
|
||||
|
||||
sii9022: sii9022@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sii902x_hdmi>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
enable-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
sii9022_in_rgb: endpoint {
|
||||
remote-endpoint = <&rgb_out_sii9022>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of pcie2x1/pdm_codec and rgb are multiplexed
|
||||
*/
|
||||
&pcie2x1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pdm_codec {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
sii902x {
|
||||
sii902x_hdmi: sii902x-hdmi {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vo_pins>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rgb_out_sii9022: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sii9022_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rgb_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_rgb {
|
||||
status = "disabled";
|
||||
connect = <&vp0_out_rgb>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The pins of sai0/vcc_mipicsi0/u2phy_host and rgb are multiplexed
|
||||
*/
|
||||
&sai0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&u2phy_host {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vcc5v0_usb_host {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vcc_mipicsi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&video_phy {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -370,21 +370,21 @@
|
||||
i2s0m0_lrck: i2s0m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s0_lrck_m0 */
|
||||
<3 RK_PA4 1 &pcfg_pull_none>;
|
||||
<3 RK_PA4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m0_mclk: i2s0m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_mclk_m0 */
|
||||
<3 RK_PA2 1 &pcfg_pull_none>;
|
||||
<3 RK_PA2 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m0_sclk: i2s0m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_sclk_m0 */
|
||||
<3 RK_PA3 1 &pcfg_pull_none>;
|
||||
<3 RK_PA3 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -447,21 +447,21 @@
|
||||
i2s0m1_lrck: i2s0m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s0_lrck_m1 */
|
||||
<1 RK_PC4 3 &pcfg_pull_none>;
|
||||
<1 RK_PC4 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m1_mclk: i2s0m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_mclk_m1 */
|
||||
<1 RK_PC6 3 &pcfg_pull_none>;
|
||||
<1 RK_PC6 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0m1_sclk: i2s0m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_sclk_m1 */
|
||||
<1 RK_PC5 3 &pcfg_pull_none>;
|
||||
<1 RK_PC5 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -526,21 +526,21 @@
|
||||
i2s1m0_lrck: i2s1m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s1_lrck_m0 */
|
||||
<3 RK_PC6 2 &pcfg_pull_none>;
|
||||
<3 RK_PC6 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_mclk: i2s1m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1_mclk_m0 */
|
||||
<3 RK_PC4 2 &pcfg_pull_none>;
|
||||
<3 RK_PC4 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclk: i2s1m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s1_sclk_m0 */
|
||||
<3 RK_PC5 2 &pcfg_pull_none>;
|
||||
<3 RK_PC5 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -603,21 +603,21 @@
|
||||
i2s1m1_lrck: i2s1m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s1_lrck_m1 */
|
||||
<3 RK_PB4 1 &pcfg_pull_none>;
|
||||
<3 RK_PB4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_mclk: i2s1m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1_mclk_m1 */
|
||||
<3 RK_PB2 1 &pcfg_pull_none>;
|
||||
<3 RK_PB2 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_sclk: i2s1m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s1_sclk_m1 */
|
||||
<3 RK_PB3 1 &pcfg_pull_none>;
|
||||
<3 RK_PB3 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -682,21 +682,21 @@
|
||||
i2s2m0_lrck: i2s2m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s2_lrck_m0 */
|
||||
<1 RK_PD6 1 &pcfg_pull_none>;
|
||||
<1 RK_PD6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_mclk: i2s2m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2_mclk_m0 */
|
||||
<2 RK_PA1 1 &pcfg_pull_none>;
|
||||
<2 RK_PA1 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sclk: i2s2m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s2_sclk_m0 */
|
||||
<1 RK_PD5 1 &pcfg_pull_none>;
|
||||
<1 RK_PD5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -717,21 +717,21 @@
|
||||
i2s2m1_lrck: i2s2m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s2_lrck_m1 */
|
||||
<4 RK_PA1 3 &pcfg_pull_none>;
|
||||
<4 RK_PA1 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_mclk: i2s2m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2_mclk_m1 */
|
||||
<3 RK_PD6 3 &pcfg_pull_none>;
|
||||
<3 RK_PD6 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_sclk: i2s2m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s2_sclk_m1 */
|
||||
<4 RK_PB1 4 &pcfg_pull_none>;
|
||||
<4 RK_PB1 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
|
||||
@@ -917,35 +917,35 @@
|
||||
i2s1m0_lrckrx: i2s1m0-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrckrx */
|
||||
<1 RK_PA6 1 &pcfg_pull_none>;
|
||||
<1 RK_PA6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_lrcktx: i2s1m0-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrcktx */
|
||||
<1 RK_PA5 1 &pcfg_pull_none>;
|
||||
<1 RK_PA5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_mclk: i2s1m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_mclk */
|
||||
<1 RK_PA2 1 &pcfg_pull_none>;
|
||||
<1 RK_PA2 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclkrx: i2s1m0-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclkrx */
|
||||
<1 RK_PA4 1 &pcfg_pull_none>;
|
||||
<1 RK_PA4 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclktx: i2s1m0-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclktx */
|
||||
<1 RK_PA3 1 &pcfg_pull_none>;
|
||||
<1 RK_PA3 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1008,35 +1008,35 @@
|
||||
i2s1m1_lrckrx: i2s1m1-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_lrckrx */
|
||||
<4 RK_PA7 5 &pcfg_pull_none>;
|
||||
<4 RK_PA7 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_lrcktx: i2s1m1-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_lrcktx */
|
||||
<3 RK_PD0 4 &pcfg_pull_none>;
|
||||
<3 RK_PD0 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_mclk: i2s1m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_mclk */
|
||||
<3 RK_PC6 4 &pcfg_pull_none>;
|
||||
<3 RK_PC6 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_sclkrx: i2s1m1-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_sclkrx */
|
||||
<4 RK_PA6 5 &pcfg_pull_none>;
|
||||
<4 RK_PA6 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_sclktx: i2s1m1-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_sclktx */
|
||||
<3 RK_PC7 4 &pcfg_pull_none>;
|
||||
<3 RK_PC7 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1099,35 +1099,35 @@
|
||||
i2s1m2_lrckrx: i2s1m2-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m2_lrckrx */
|
||||
<3 RK_PC5 5 &pcfg_pull_none>;
|
||||
<3 RK_PC5 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m2_lrcktx: i2s1m2-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m2_lrcktx */
|
||||
<2 RK_PD2 5 &pcfg_pull_none>;
|
||||
<2 RK_PD2 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m2_mclk: i2s1m2-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m2_mclk */
|
||||
<2 RK_PD0 5 &pcfg_pull_none>;
|
||||
<2 RK_PD0 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m2_sclkrx: i2s1m2-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m2_sclkrx */
|
||||
<3 RK_PC3 5 &pcfg_pull_none>;
|
||||
<3 RK_PC3 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m2_sclktx: i2s1m2-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m2_sclktx */
|
||||
<2 RK_PD1 5 &pcfg_pull_none>;
|
||||
<2 RK_PD1 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1192,35 +1192,35 @@
|
||||
i2s2m0_lrckrx: i2s2m0-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_lrckrx */
|
||||
<2 RK_PC0 1 &pcfg_pull_none>;
|
||||
<2 RK_PC0 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_lrcktx: i2s2m0-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_lrcktx */
|
||||
<2 RK_PC3 1 &pcfg_pull_none>;
|
||||
<2 RK_PC3 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_mclk: i2s2m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_mclk */
|
||||
<2 RK_PC1 1 &pcfg_pull_none>;
|
||||
<2 RK_PC1 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sclkrx: i2s2m0-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_sclkrx */
|
||||
<2 RK_PB7 1 &pcfg_pull_none>;
|
||||
<2 RK_PB7 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sclktx: i2s2m0-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_sclktx */
|
||||
<2 RK_PC2 1 &pcfg_pull_none>;
|
||||
<2 RK_PC2 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1241,35 +1241,35 @@
|
||||
i2s2m1_lrckrx: i2s2m1-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_lrckrx */
|
||||
<4 RK_PA5 5 &pcfg_pull_none>;
|
||||
<4 RK_PA5 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_lrcktx: i2s2m1-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_lrcktx */
|
||||
<4 RK_PA4 5 &pcfg_pull_none>;
|
||||
<4 RK_PA4 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_mclk: i2s2m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_mclk */
|
||||
<4 RK_PB6 5 &pcfg_pull_none>;
|
||||
<4 RK_PB6 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_sclkrx: i2s2m1-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_sclkrx */
|
||||
<4 RK_PC1 5 &pcfg_pull_none>;
|
||||
<4 RK_PC1 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_sclktx: i2s2m1-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_sclktx */
|
||||
<4 RK_PB7 4 &pcfg_pull_none>;
|
||||
<4 RK_PB7 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1292,21 +1292,21 @@
|
||||
i2s3m0_lrck: i2s3m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s3m0_lrck */
|
||||
<3 RK_PA4 4 &pcfg_pull_none>;
|
||||
<3 RK_PA4 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3m0_mclk: i2s3m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s3m0_mclk */
|
||||
<3 RK_PA2 4 &pcfg_pull_none>;
|
||||
<3 RK_PA2 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3m0_sclk: i2s3m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s3m0_sclk */
|
||||
<3 RK_PA3 4 &pcfg_pull_none>;
|
||||
<3 RK_PA3 4 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1327,21 +1327,21 @@
|
||||
i2s3m1_lrck: i2s3m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s3m1_lrck */
|
||||
<4 RK_PC4 5 &pcfg_pull_none>;
|
||||
<4 RK_PC4 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3m1_mclk: i2s3m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s3m1_mclk */
|
||||
<4 RK_PC2 5 &pcfg_pull_none>;
|
||||
<4 RK_PC2 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3m1_sclk: i2s3m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s3m1_sclk */
|
||||
<4 RK_PC3 5 &pcfg_pull_none>;
|
||||
<4 RK_PC3 5 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
|
||||
15
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-android.dts
Normal file
15
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-android.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3568-toybrick-sd0.dtsi"
|
||||
#include "rk3568-android.dtsi"
|
||||
//#include "rk3568-toybrick-sd0-mipi-tx0.dtsi"
|
||||
/delete-node/ &board_id;
|
||||
/ {
|
||||
model = "Rockchip RK3568 Toybrick SD0 Board";
|
||||
compatible = "rockchip,rk3568-toybrick-sd0-linux","rockchip,rk3568";
|
||||
};
|
||||
15
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-linux.dts
Normal file
15
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-linux.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3568-toybrick-sd0.dtsi"
|
||||
#include "rk3568-linux.dtsi"
|
||||
//#include "rk3568-toybrick-sd0-mipi-tx0.dtsi"
|
||||
/delete-node/ &board_id;
|
||||
/ {
|
||||
model = "Rockchip RK3568 Toybrick SD0 Board";
|
||||
compatible = "rockchip,rk3568-toybrick-sd0-linux","rockchip,rk3568";
|
||||
};
|
||||
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3568-toybrick-sd0-mipi-tx0", "rockchip,rk3568";
|
||||
};
|
||||
|
||||
/*
|
||||
* mipi_dphy0 needs to be enabled
|
||||
* when dsi0 is enabled
|
||||
*/
|
||||
&backlight {
|
||||
status = "okay";
|
||||
pwms = <&pwm14 0 25000 0>;
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0_in_vp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi0_in_vp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0_panel {
|
||||
power-supply = <&vcc3v3_lcd0_n>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
power-supply = <&vcc3v3_lcd0_n>;
|
||||
gt1x: gt1x@14 {
|
||||
compatible = "goodix,gt1x";
|
||||
status = "okay";
|
||||
reg = <0x14>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_pin>;
|
||||
goodix,rst-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
goodix,irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm14{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi0 {
|
||||
status = "okay";
|
||||
connect = <&vp1_out_dsi0>;
|
||||
};
|
||||
|
||||
&vcc3v3_lcd0_n {
|
||||
gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
&video_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
touch {
|
||||
touch_pin: touch-pin {
|
||||
rockchip,pins =
|
||||
<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
607
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi
Normal file
607
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi
Normal file
@@ -0,0 +1,607 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
#include "rk3568-toybrick.dtsi"
|
||||
|
||||
/delete-node/ &adc_keys;
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3568-toybrick-sd0", "rockchip,rk3568";
|
||||
|
||||
bt-sound {
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "dsp_a";
|
||||
simple-audio-card,bitclock-inversion = <1>;
|
||||
simple-audio-card,mclk-fs = <512>;
|
||||
simple-audio-card,name = "rockchip,bt";
|
||||
#simple-audio-card,bitclock-master = <&sound2_master>;
|
||||
#simple-audio-card,frame-master = <&sound2_master>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s2_2ch>;
|
||||
};
|
||||
sound2_master:simple-audio-card,codec {
|
||||
#sound-dai-cells = <0>;
|
||||
sound-dai = <&bt_sco>;
|
||||
};
|
||||
};
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_3v3: gpio-regulator {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "pcie30_3v3";
|
||||
regulator-min-microvolt = <100000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0x1>;
|
||||
states = <100000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
rk_headset: rk-headset {
|
||||
compatible = "rockchip_headset";
|
||||
headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_det>;
|
||||
io-channels = <&saradc 2>;
|
||||
};
|
||||
|
||||
vcc2v5_sys: vcc2v5-ddr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc2v5-sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: gpio-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_bu: vcc3v3-bu {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_bu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_camera: vcc-camera-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camera_pwr>;
|
||||
regulator-name = "vcc_camera";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
regulator-name = "vcc5v0_otg";
|
||||
};
|
||||
};
|
||||
|
||||
&bus_npu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy0_us {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_usq {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psq {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&imx415_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
mipi_in_ucam1: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&ov50c40_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&isp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>, <25000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus
|
||||
ð1m1_pins>;
|
||||
|
||||
tx_delay = <0x47>;
|
||||
rx_delay = <0x28>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2_2ch {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
regulators {
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s1_8ch {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
rockchip,clk-trcm = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1m0_sclktx
|
||||
&i2s1m0_lrcktx
|
||||
&i2s1m0_sdo0
|
||||
&i2s1m0_sdi0>;
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "hym8563";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2m1_xfer>;
|
||||
imx415: imx415@1a {
|
||||
compatible = "sony,imx415";
|
||||
reg = <0x1a>;
|
||||
clocks = <&cru CLK_CIF_OUT>;
|
||||
clock-names = "xvclk";
|
||||
power-domains = <&power RK3568_PD_VI>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cif_clk>;
|
||||
// must be high at last
|
||||
power-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
// must be high at last do at vcc_camera
|
||||
//reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "CMK-OT2022-PX1";
|
||||
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20-RK3568";
|
||||
//lens-focus = <&cam_ircut0>;
|
||||
port {
|
||||
imx415_out: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aw8601: aw8601@c {
|
||||
compatible = "awinic,aw8601";
|
||||
status = "okay";
|
||||
reg = <0x0c>;
|
||||
rockchip,vcm-start-current = <56>;
|
||||
rockchip,vcm-rated-current = <96>;
|
||||
rockchip,vcm-step-mode = <4>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
};
|
||||
|
||||
otp_eeprom: otp_eeprom@50 {
|
||||
compatible = "rk,otp_eeprom";
|
||||
status = "okay";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
ov50c40: ov50c40@36 {
|
||||
compatible = "ovti,ov50c40";
|
||||
reg = <0x36>;
|
||||
clocks = <&cru CLK_CIF_OUT>;
|
||||
clock-names = "xvclk";
|
||||
power-domains = <&power RK3568_PD_VI>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cif_clk>;
|
||||
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;// must be high at last
|
||||
reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;// must be high at last
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "HZGA06";
|
||||
rockchip,camera-module-lens-name = "ZE0082C1-RK3568";
|
||||
eeprom-ctrl = <&otp_eeprom>;
|
||||
lens-focus = <&aw8601>;
|
||||
port {
|
||||
ov50c40_out: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam1>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
status = "okay";
|
||||
compatible = "gpio-leds";
|
||||
work_led: work {
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
clocks = <&cru CLK_MAC1_OUT>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtl8111_isolate>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&pcie30_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&reserved_memory {
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
inactive;
|
||||
reusable;
|
||||
reg = <0x0 0x10000000 0x0 0x08000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
&rkisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_vir0 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp0_in: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csidphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rockchip_suspend {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rknpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <200>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
||||
};
|
||||
|
||||
&video_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&video_phy1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wireless_wlan {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&wireless_bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
//wifi-bt-power-toggle;
|
||||
uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart1m0_rtsn>;
|
||||
pinctrl-1 = <&uart1_pin>;
|
||||
BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
camera_pwr: camera-pwr {
|
||||
rockchip,pins =
|
||||
/* camera power en */
|
||||
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
headphone {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s1 {
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_lrckrx: i2s1m0-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrckrx */
|
||||
<1 RK_PA6 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_lrcktx: i2s1m0-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrcktx */
|
||||
<1 RK_PA5 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_mclk: i2s1m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_mclk */
|
||||
<1 RK_PA2 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclkrx: i2s1m0-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclkrx */
|
||||
<1 RK_PA4 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclktx: i2s1m0-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclktx */
|
||||
<1 RK_PA3 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi0: i2s1m0-sdi0 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi0 */
|
||||
<1 RK_PB3 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi1: i2s1m0-sdi1 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi1 */
|
||||
<1 RK_PB2 2 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi2: i2s1m0-sdi2 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi2 */
|
||||
<1 RK_PB1 2 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi3: i2s1m0-sdi3 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi3 */
|
||||
<1 RK_PB0 2 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdo0: i2s1m0-sdo0 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdo0 */
|
||||
<1 RK_PA7 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rtl8111 {
|
||||
rtl8111_isolate: rtl8111-isolate {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart1_pin: uart1-pin {
|
||||
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
13
arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-android.dts
Normal file
13
arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-android.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3568-toybrick-x0.dtsi"
|
||||
#include "rk3568-android.dtsi"
|
||||
/ {
|
||||
compatible = "rockchip,rk3568-toybrick-x0-android","rockchip,rk3568";
|
||||
};
|
||||
|
||||
13
arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-linux.dts
Normal file
13
arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0-linux.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3568-toybrick-x0.dtsi"
|
||||
#include "rk3568-linux.dtsi"
|
||||
/delete-node/ &board_id;
|
||||
/ {
|
||||
compatible = "rockchip,rk3568-toybrick-x0-linux","rockchip,rk3568";
|
||||
};
|
||||
725
arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0.dtsi
Normal file
725
arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0.dtsi
Normal file
@@ -0,0 +1,725 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
#include "rk3568-toybrick.dtsi"
|
||||
|
||||
/delete-node/ &adc_keys;
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3568-toybrick", "rockchip,rk3568";
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 0>;
|
||||
io-channel-names = "buttons";
|
||||
poll-interval = <100>;
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
|
||||
menu-key {
|
||||
linux,code = <KEY_MENU>;
|
||||
label = "menu";
|
||||
press-threshold-microvolt = <1250000>;
|
||||
};
|
||||
|
||||
mute-key {
|
||||
linux,code = <KEY_MUTE>;
|
||||
label = "mute";
|
||||
press-threshold-microvolt = <850000>;
|
||||
};
|
||||
|
||||
vol-down-key {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
label = "volume down";
|
||||
press-threshold-microvolt = <400000>;
|
||||
};
|
||||
|
||||
vol-up-key {
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
label = "volume up";
|
||||
press-threshold-microvolt = <20000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_leds: gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
led@1 {
|
||||
gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
label = "blue"; // Blue LED
|
||||
retain-state-suspended;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
label = "red"; // Red LED
|
||||
retain-state-suspended;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
label = "green"; // Green LED
|
||||
retain-state-suspended;
|
||||
};
|
||||
};
|
||||
|
||||
pcie20_3v3: gpio-regulator {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "pcie20_3v3";
|
||||
regulator-min-microvolt = <100000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0x1>;
|
||||
states = <100000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_3v3: gpio-regulator {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "pcie30_3v3";
|
||||
regulator-min-microvolt = <100000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0x1>;
|
||||
states = <100000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
rk_headset: rk-headset {
|
||||
compatible = "rockchip_headset";
|
||||
headset_gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hp_det>;
|
||||
io-channels = <&saradc 1>;
|
||||
};
|
||||
|
||||
rk809_sound_micarray: rk809-sound-micarray {
|
||||
status = "disabled";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "rockchip,rk809-codec";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,dai-link@0 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&rk809_codec 0>;
|
||||
};
|
||||
};
|
||||
simple-audio-card,dai-link@1 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&es7210>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rt5672-sound {
|
||||
compatible = "rockchip-rt5670";
|
||||
status = "disabled";
|
||||
dais {
|
||||
dai0 {
|
||||
audio-codec = <&rt5670>;
|
||||
audio-controller = <&i2s1_8ch>;
|
||||
format = "i2s";
|
||||
};
|
||||
dai1 {
|
||||
audio-codec = <&rt5670>;
|
||||
audio-controller = <&i2s1_8ch>;
|
||||
format = "i2s";
|
||||
};
|
||||
dai2 {
|
||||
audio-codec = <&es7210>;
|
||||
audio-controller = <&i2s1_8ch>;
|
||||
format = "i2s";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vcc2v5_sys: vcc2v5-ddr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc2v5-sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_camera: vcc-camera-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camera_pwr>;
|
||||
regulator-name = "vcc_camera";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_bu: vcc3v3-bu {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_bu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_us {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_usq {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psq {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_in_ucam0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&ucam_out0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
mipi_in_ucam1: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&gc8034_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
mipi_in_ucam2: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&ov5695_out>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&isp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
|
||||
tx_delay = <0x37>;
|
||||
rx_delay = <0x2e>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
|
||||
tx_delay = <0x47>;
|
||||
rx_delay = <0x28>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
rt5670: rt5670@1c {
|
||||
status = "okay";
|
||||
#sound-dai-cell = <0>;
|
||||
compatible = "realtek,rt5670";
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
es7210: es7210@40 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "MicArray_0";
|
||||
reg = <0x40>;
|
||||
clocks = <&cru I2S1_MCLKOUT_RX>;//csqerr
|
||||
clock-names = "mclk";
|
||||
};
|
||||
|
||||
es7210_1: es7210@42 {
|
||||
compatible = "MicArray_1";
|
||||
reg = <0x42>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
gc8034: gc8034@37 {
|
||||
compatible = "galaxycore,gc8034";
|
||||
reg = <0x37>;
|
||||
clocks = <&cru CLK_CIF_OUT>;//CLK_CAM0_OUT>;
|
||||
clock-names = "xvclk";
|
||||
power-domains = <&power RK3568_PD_VI>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cif_clk>;
|
||||
reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "RK-CMK-8M-2-v1";
|
||||
rockchip,camera-module-lens-name = "CK8401";
|
||||
port {
|
||||
gc8034_out: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam1>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ov9750_1: ov9750_1@36 {
|
||||
compatible = "ovti,ov9750";
|
||||
reg = <0x36>;
|
||||
clocks = <&cru CLK_CIF_OUT>;
|
||||
clock-names = "xvclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cif_clk>;
|
||||
power-domains = <&power RK3568_PD_VI>;
|
||||
reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "CMK-OT0854-FV1";
|
||||
rockchip,camera-module-lens-name = "CHT-842B-MD";
|
||||
port {
|
||||
ucam_out0: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ov5695: ov5695@36 {
|
||||
status = "okay";
|
||||
compatible = "ovti,ov5695";
|
||||
reg = <0x36>;
|
||||
clocks = <&cru CLK_CIF_OUT>;
|
||||
clock-names = "xvclk";
|
||||
power-domains = <&power RK3568_PD_VI>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cif_clk>;
|
||||
reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "TongJu";
|
||||
rockchip,camera-module-lens-name = "CHT842-MD";
|
||||
port {
|
||||
ov5695_out: endpoint {
|
||||
remote-endpoint = <&mipi_in_ucam2>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
gs_mxc6655xa: gs_mxc6655xa@15 {
|
||||
status = "okay";
|
||||
compatible = "gs_mxc6655xa";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mxc6655xa_irq_pin>;
|
||||
reg = <0x15>;
|
||||
irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
|
||||
irq_enable = <0>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_ACCEL>;
|
||||
power-off-in-suspend = <1>;
|
||||
layout = <1>;
|
||||
};
|
||||
|
||||
mxc6655xa: mxc6655xa@15 {
|
||||
status = "disabled";
|
||||
compatible = "gs_mxc6655xa";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mxc6655xa_irq_pin>;
|
||||
reg = <0x15>;
|
||||
irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
|
||||
irq_enable = <0>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_ACCEL>;
|
||||
power-off-in-suspend = <1>;
|
||||
layout = <1>;
|
||||
};
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2s1_8ch {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
rockchip,clk-trcm = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1m0_sclktx
|
||||
&i2s1m0_sclkrx
|
||||
&i2s1m0_lrcktx
|
||||
&i2s1m0_sclkrx
|
||||
&i2s1m0_lrckrx
|
||||
&i2s1m0_sdo0
|
||||
&i2s1m0_sdi0
|
||||
&i2s1m0_sdi1
|
||||
&i2s1m0_sdi2
|
||||
&i2s1m0_sdi3>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&pcie30_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rk809_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkisp_vir0 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp0_in: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csidphy_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
|
||||
};
|
||||
|
||||
&vcc3v3_lcd0_n {
|
||||
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
&vcc3v3_lcd1_n {
|
||||
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
&video_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&video_phy1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wireless_wlan {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&wireless_bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
//wifi-bt-power-toggle;
|
||||
uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart8m0_rtsn>;
|
||||
pinctrl-1 = <&uart8_pin>;
|
||||
BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
camera_pwr: camera-pwr {
|
||||
rockchip,pins =
|
||||
/* camera power en */
|
||||
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
headphone {
|
||||
hp_det: hp-det {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s1 {
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_lrckrx: i2s1m0-lrckrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrckrx */
|
||||
<1 RK_PA6 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_lrcktx: i2s1m0-lrcktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrcktx */
|
||||
<1 RK_PA5 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_mclk: i2s1m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_mclk */
|
||||
<1 RK_PA2 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclkrx: i2s1m0-sclkrx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclkrx */
|
||||
<1 RK_PA4 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclktx: i2s1m0-sclktx {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclktx */
|
||||
<1 RK_PA3 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi0: i2s1m0-sdi0 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi0 */
|
||||
<1 RK_PB3 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi1: i2s1m0-sdi1 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi1 */
|
||||
<1 RK_PB2 2 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi2: i2s1m0-sdi2 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi2 */
|
||||
<1 RK_PB1 2 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdi3: i2s1m0-sdi3 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdi3 */
|
||||
<1 RK_PB0 2 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sdo0: i2s1m0-sdo0 {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sdo0 */
|
||||
<1 RK_PA7 1 &pcfg_pull_up_drv_level_4>;
|
||||
};
|
||||
};
|
||||
|
||||
leds_pin: leds-pin {
|
||||
rockchip,pins =
|
||||
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
mxc6655xa {
|
||||
mxc6655xa_irq_pin: mxc6655xa_irq_pin {
|
||||
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart8_pin: uart8-pin {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
1862
arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi
Normal file
1862
arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@@ -558,6 +558,8 @@
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -610,6 +612,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie30x4 {
|
||||
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
|
||||
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
rtl8111 {
|
||||
rtl8111_isolate: rtl8111-isolate {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
||||
@@ -385,6 +385,8 @@
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -414,6 +416,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie30x4 {
|
||||
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
|
||||
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
|
||||
@@ -1044,6 +1044,8 @@
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -1073,6 +1075,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie30x4 {
|
||||
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
|
||||
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
rtl8111 {
|
||||
rtl8111_isolate: rtl8111-isolate {
|
||||
rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
||||
@@ -230,9 +230,19 @@
|
||||
num-lanes = <2>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcie30x4 {
|
||||
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
|
||||
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm9 {
|
||||
pinctrl-0 = <&pwm9m2_pins>;
|
||||
status = "okay";
|
||||
|
||||
@@ -627,6 +627,8 @@
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -679,6 +681,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie30x4 {
|
||||
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
|
||||
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
||||
@@ -111,8 +111,3 @@
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Assign VOP_ACLK to 750MHZ for 8K */
|
||||
&vop {
|
||||
assigned-clock-rates = <750000000>;
|
||||
};
|
||||
|
||||
@@ -426,6 +426,8 @@
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -694,6 +696,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie30x4 {
|
||||
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
|
||||
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
rtc {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
||||
@@ -260,25 +260,34 @@
|
||||
};
|
||||
|
||||
i2s2 {
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_idle: i2s2m0-idle {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_lrck_gpio */
|
||||
<2 RK_PC0 0 &pcfg_pull_none>,
|
||||
/* i2s2m0_sclk_gpio */
|
||||
<2 RK_PB7 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_lrck: i2s2m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_lrck */
|
||||
<2 RK_PC0 2 &pcfg_pull_none>;
|
||||
<2 RK_PC0 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_mclk: i2s2m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_mclk */
|
||||
<2 RK_PB6 2 &pcfg_pull_none>;
|
||||
<2 RK_PB6 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sclk: i2s2m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_sclk */
|
||||
<2 RK_PB7 2 &pcfg_pull_none>;
|
||||
<2 RK_PB7 2 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
max96722_osc: max96722-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "max96722-osc";
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_dphy0_in_max96722: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&max96722_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi2_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m3_xfer>, <&max96722_errb>, <&max96722_lock>;
|
||||
|
||||
max96722: max96722@29 {
|
||||
compatible = "max96722";
|
||||
status = "okay";
|
||||
reg = <0x29>;
|
||||
clock-names = "xvclk";
|
||||
clocks = <&max96722_osc 0>;
|
||||
power-domains = <&power RK3588_PD_VI>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
power-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
pocen-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
link-mask = <0x0F>;
|
||||
auto-init-deskew-mask = <0x03>;
|
||||
frame-sync-period = <0>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "max96722";
|
||||
rockchip,camera-module-lens-name = "max96722";
|
||||
|
||||
port {
|
||||
max96722_out: endpoint {
|
||||
remote-endpoint = <&mipi_dphy0_in_max96722>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi2_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi2_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi2_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi2_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds2 {
|
||||
status = "okay";
|
||||
/* parameters for do cif reset detecting:
|
||||
* index0: monitor mode,
|
||||
0 for idle,
|
||||
1 for continue,
|
||||
2 for trigger,
|
||||
3 for hotplug (for nextchip)
|
||||
* index1: the frame id to start timer,
|
||||
min is 2
|
||||
* index2: frame num of monitoring cycle
|
||||
* index3: err time for keep monitoring
|
||||
after finding out err (ms)
|
||||
* index4: csi2 err reference val for resetting
|
||||
*/
|
||||
rockchip,cif-monitor = <3 2 1 1000 5>;
|
||||
|
||||
port {
|
||||
cif_mipi2_in: endpoint {
|
||||
remote-endpoint = <&mipi2_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
rockchip,android-usb-camerahal-enable;
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
max96722 {
|
||||
max96722_errb: max96722-errb {
|
||||
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
max96722_lock: max96722-lock {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -28,13 +28,13 @@
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&bt_sco>;
|
||||
sound-dai = <&bt_sco 1>;
|
||||
};
|
||||
};
|
||||
|
||||
bt_sco: bt-sco {
|
||||
compatible = "delta,dfbmcs320";
|
||||
#sound-dai-cells = <0>;
|
||||
#sound-dai-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -27,13 +27,13 @@
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&bt_sco>;
|
||||
sound-dai = <&bt_sco 1>;
|
||||
};
|
||||
};
|
||||
|
||||
bt_sco: bt-sco {
|
||||
compatible = "delta,dfbmcs320";
|
||||
#sound-dai-cells = <0>;
|
||||
#sound-dai-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -163,7 +163,7 @@
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
pinctrl-names = "phydisb";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
|
||||
@@ -26,13 +26,13 @@
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&bt_sco>;
|
||||
sound-dai = <&bt_sco 1>;
|
||||
};
|
||||
};
|
||||
|
||||
bt_sco: bt-sco {
|
||||
compatible = "delta,dfbmcs320";
|
||||
#sound-dai-cells = <0>;
|
||||
#sound-dai-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
gpio-keys {
|
||||
|
||||
@@ -174,7 +174,7 @@
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
pinctrl-names = "phydisb";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
|
||||
@@ -7,37 +7,60 @@
|
||||
#include "rk3588.dtsi"
|
||||
|
||||
&cluster0_opp_table {
|
||||
/delete-node/ opp-1608000000;
|
||||
/delete-node/ opp-1704000000;
|
||||
/delete-node/ opp-1800000000;
|
||||
/*
|
||||
* The Max frequency is 1296MHz in default normal mode.
|
||||
* The Max frequency is 1704MHz in overdrive mode,
|
||||
* but under the overdrive mode for a long time,
|
||||
* the chipset may shorten the lifetime,
|
||||
* especially in high temperature condition.
|
||||
*/
|
||||
/delete-node/ opp-j-m-1416000000;
|
||||
/delete-node/ opp-j-m-1608000000;
|
||||
/delete-node/ opp-j-m-1704000000;
|
||||
};
|
||||
|
||||
&cluster1_opp_table {
|
||||
/delete-node/ opp-1800000000;
|
||||
/delete-node/ opp-2016000000;
|
||||
/delete-node/ opp-2208000000;
|
||||
/delete-node/ opp-2256000000;
|
||||
/delete-node/ opp-2304000000;
|
||||
/delete-node/ opp-2352000000;
|
||||
/delete-node/ opp-2400000000;
|
||||
/*
|
||||
* The Max frequency is 1608MHz in default normal mode.
|
||||
* The Max frequency is 2016MHz in overdrive mode,
|
||||
* but under the overdrive mode for a long time,
|
||||
* the chipset may shorten the lifetime,
|
||||
* especially in high temperature condition.
|
||||
*/
|
||||
/delete-node/ opp-j-m-1800000000;
|
||||
/delete-node/ opp-j-m-2016000000;
|
||||
};
|
||||
|
||||
&cluster2_opp_table {
|
||||
/delete-node/ opp-1800000000;
|
||||
/delete-node/ opp-2016000000;
|
||||
/delete-node/ opp-2208000000;
|
||||
/delete-node/ opp-2256000000;
|
||||
/delete-node/ opp-2304000000;
|
||||
/delete-node/ opp-2352000000;
|
||||
/delete-node/ opp-2400000000;
|
||||
/*
|
||||
* The Max frequency is 1608MHz in default normal mode.
|
||||
* The Max frequency is 2016MHz in overdrive mode,
|
||||
* but under the overdrive mode for a long time,
|
||||
* the chipset may shorten the lifetime,
|
||||
* especially in high temperature condition.
|
||||
*/
|
||||
/delete-node/ opp-j-m-1800000000;
|
||||
/delete-node/ opp-j-m-2016000000;
|
||||
};
|
||||
|
||||
&gpu_opp_table {
|
||||
/delete-node/ opp-900000000;
|
||||
/delete-node/ opp-1000000000;
|
||||
/*
|
||||
* The Max frequency is 700MHz in default normal mode.
|
||||
* The Max frequency is 850MHz in overdrive mode,
|
||||
* but under the overdrive mode for a long time,
|
||||
* the chipset may shorten the lifetime,
|
||||
* especially in high temperature condition.
|
||||
*/
|
||||
/delete-node/ opp-j-850000000;
|
||||
};
|
||||
|
||||
&npu_opp_table {
|
||||
/delete-node/ opp-900000000;
|
||||
/delete-node/ opp-1000000000;
|
||||
/*
|
||||
* The Max frequency is 800MHz in default normal mode.
|
||||
* The Max frequency is 950MHz in overdrive mode,
|
||||
* but under the overdrive mode for a long time,
|
||||
* the chipset may shorten the lifetime,
|
||||
* especially in high temperature condition.
|
||||
*/
|
||||
/delete-node/ opp-j-m-950000000;
|
||||
};
|
||||
|
||||
@@ -5,23 +5,3 @@
|
||||
*/
|
||||
|
||||
#include "rk3588.dtsi"
|
||||
|
||||
&cluster0_opp_table {
|
||||
/delete-node/ opp-1800000000;
|
||||
};
|
||||
|
||||
&cluster1_opp_table {
|
||||
/delete-node/ opp-2208000000;
|
||||
/delete-node/ opp-2256000000;
|
||||
/delete-node/ opp-2304000000;
|
||||
/delete-node/ opp-2352000000;
|
||||
/delete-node/ opp-2400000000;
|
||||
};
|
||||
|
||||
&cluster2_opp_table {
|
||||
/delete-node/ opp-2208000000;
|
||||
/delete-node/ opp-2256000000;
|
||||
/delete-node/ opp-2304000000;
|
||||
/delete-node/ opp-2352000000;
|
||||
/delete-node/ opp-2400000000;
|
||||
};
|
||||
|
||||
@@ -1129,25 +1129,34 @@
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
/omit-if-no-ref/
|
||||
i2s0_idle: i2s0-idle {
|
||||
rockchip,pins =
|
||||
/* i2s0_lrck_gpio */
|
||||
<1 RK_PC5 0 &pcfg_pull_none>,
|
||||
/* i2s0_sclk_gpio */
|
||||
<1 RK_PC3 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0_lrck: i2s0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s0_lrck */
|
||||
<1 RK_PC5 1 &pcfg_pull_none>;
|
||||
<1 RK_PC5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0_mclk: i2s0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_mclk */
|
||||
<1 RK_PC2 1 &pcfg_pull_none>;
|
||||
<1 RK_PC2 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s0_sclk: i2s0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s0_sclk */
|
||||
<1 RK_PC3 1 &pcfg_pull_none>;
|
||||
<1 RK_PC3 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1212,21 +1221,21 @@
|
||||
i2s1m0_lrck: i2s1m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_lrck */
|
||||
<4 RK_PA2 3 &pcfg_pull_none>;
|
||||
<4 RK_PA2 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_mclk: i2s1m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_mclk */
|
||||
<4 RK_PA0 3 &pcfg_pull_none>;
|
||||
<4 RK_PA0 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m0_sclk: i2s1m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m0_sclk */
|
||||
<4 RK_PA1 3 &pcfg_pull_none>;
|
||||
<4 RK_PA1 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1288,21 +1297,21 @@
|
||||
i2s1m1_lrck: i2s1m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_lrck */
|
||||
<0 RK_PB7 1 &pcfg_pull_none>;
|
||||
<0 RK_PB7 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_mclk: i2s1m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_mclk */
|
||||
<0 RK_PB5 1 &pcfg_pull_none>;
|
||||
<0 RK_PB5 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s1m1_sclk: i2s1m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s1m1_sclk */
|
||||
<0 RK_PB6 1 &pcfg_pull_none>;
|
||||
<0 RK_PB6 1 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1363,25 +1372,34 @@
|
||||
};
|
||||
|
||||
i2s2 {
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_idle: i2s2m1-idle {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_lrck_gpio */
|
||||
<3 RK_PB6 0 &pcfg_pull_none>,
|
||||
/* i2s2m1_sclk_gpio */
|
||||
<3 RK_PB5 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_lrck: i2s2m1-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_lrck */
|
||||
<3 RK_PB6 3 &pcfg_pull_none>;
|
||||
<3 RK_PB6 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_mclk: i2s2m1-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_mclk */
|
||||
<3 RK_PB4 3 &pcfg_pull_none>;
|
||||
<3 RK_PB4 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m1_sclk: i2s2m1-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m1_sclk */
|
||||
<3 RK_PB5 3 &pcfg_pull_none>;
|
||||
<3 RK_PB5 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1400,25 +1418,34 @@
|
||||
};
|
||||
|
||||
i2s3 {
|
||||
/omit-if-no-ref/
|
||||
i2s3_idle: i2s3-idle {
|
||||
rockchip,pins =
|
||||
/* i2s3_lrck_gpio */
|
||||
<3 RK_PA2 0 &pcfg_pull_none>,
|
||||
/* i2s3_sclk_gpio */
|
||||
<3 RK_PA1 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3_lrck: i2s3-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s3_lrck */
|
||||
<3 RK_PA2 3 &pcfg_pull_none>;
|
||||
<3 RK_PA2 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3_mclk: i2s3-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s3_mclk */
|
||||
<3 RK_PA0 3 &pcfg_pull_none>;
|
||||
<3 RK_PA0 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s3_sclk: i2s3-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s3_sclk */
|
||||
<3 RK_PA1 3 &pcfg_pull_none>;
|
||||
<3 RK_PA1 3 &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
@@ -1819,6 +1846,15 @@
|
||||
<1 RK_PC4 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm0m0_idle: pdm0m0-idle {
|
||||
rockchip,pins =
|
||||
/* pdm0m0_clk0_gpio */
|
||||
<1 RK_PC6 0 &pcfg_pull_none>,
|
||||
/* pdm0m0_clk1_gpio */
|
||||
<1 RK_PC4 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm0m0_sdi0: pdm0m0-sdi0 {
|
||||
rockchip,pins =
|
||||
@@ -1860,6 +1896,15 @@
|
||||
<0 RK_PC4 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm0m1_idle: pdm0m1-idle {
|
||||
rockchip,pins =
|
||||
/* pdm0m1_clk0_gpio */
|
||||
<0 RK_PC0 0 &pcfg_pull_none>,
|
||||
/* pdm0m1_clk1_gpio */
|
||||
<0 RK_PC4 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm0m1_sdi0: pdm0m1-sdi0 {
|
||||
rockchip,pins =
|
||||
@@ -1904,6 +1949,15 @@
|
||||
<4 RK_PD4 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm1m0_idle: pdm1m0-idle {
|
||||
rockchip,pins =
|
||||
/* pdm1m0_clk0_gpio */
|
||||
<4 RK_PD5 0 &pcfg_pull_none>,
|
||||
/* pdm1m0_clk1_gpio */
|
||||
<4 RK_PD4 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm1m0_sdi0: pdm1m0-sdi0 {
|
||||
rockchip,pins =
|
||||
@@ -1931,6 +1985,7 @@
|
||||
/* pdm1m0_sdi3 */
|
||||
<4 RK_PD0 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm1m1_clk: pdm1m1-clk {
|
||||
rockchip,pins =
|
||||
@@ -1945,6 +2000,15 @@
|
||||
<1 RK_PB3 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm1m1_idle: pdm1m1-idle {
|
||||
rockchip,pins =
|
||||
/* pdm1m1_clk0_gpio */
|
||||
<1 RK_PB4 0 &pcfg_pull_none>,
|
||||
/* pdm1m1_clk1_gpio */
|
||||
<1 RK_PB3 0 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pdm1m1_sdi0: pdm1m1-sdi0 {
|
||||
rockchip,pins =
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -689,6 +689,7 @@ CONFIG_SND_SOC=y
|
||||
CONFIG_SND_SOC_ROCKCHIP=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_PDM=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_SAI=y
|
||||
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
|
||||
|
||||
@@ -1508,7 +1508,7 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
|
||||
*class = ahci_dev_classify(ap);
|
||||
|
||||
/* re-enable FBS if disabled before */
|
||||
if (fbs_disabled)
|
||||
if (fbs_disabled || (!ata_is_host_link(link) && pp->fbs_supported))
|
||||
ahci_enable_fbs(ap);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -3004,6 +3004,10 @@ static void rockchip_dmcfreq_parse_dt(struct rockchip_dmcfreq *dmcfreq)
|
||||
if (rockchip_get_rl_map_talbe(np, "vop-pn-msch-readlatency",
|
||||
&dmcfreq->info.vop_pn_rl_tbl))
|
||||
dev_err(dev, "failed to get vop pn to msch rl\n");
|
||||
if (dmcfreq->video_4k_rate)
|
||||
dmcfreq->info.vop_4k_rate = dmcfreq->video_4k_rate;
|
||||
else if (dmcfreq->video_4k_10b_rate)
|
||||
dmcfreq->info.vop_4k_rate = dmcfreq->video_4k_10b_rate;
|
||||
|
||||
of_property_read_u32(np, "touchboost_duration",
|
||||
(u32 *)&dmcfreq->touchboostpulse_duration_val);
|
||||
|
||||
@@ -85,9 +85,9 @@ void rockchip_dmcfreq_vop_bandwidth_update(struct dmcfreq_vop_info *vop_info)
|
||||
if (!common_info)
|
||||
return;
|
||||
|
||||
dev_dbg(common_info->dev, "line bw=%u, frame bw=%u, pn=%u\n",
|
||||
dev_dbg(common_info->dev, "line bw=%u, frame bw=%u, pn=%u, pn_4k=%u\n",
|
||||
vop_info->line_bw_mbyte, vop_info->frame_bw_mbyte,
|
||||
vop_info->plane_num);
|
||||
vop_info->plane_num, vop_info->plane_num_4k);
|
||||
|
||||
if (!common_info->vop_pn_rl_tbl || !common_info->set_msch_readlatency)
|
||||
goto vop_bw_tbl;
|
||||
@@ -129,6 +129,9 @@ vop_frame_bw_tbl:
|
||||
}
|
||||
|
||||
next:
|
||||
if (vop_info->plane_num_4k && target < common_info->vop_4k_rate)
|
||||
target = common_info->vop_4k_rate;
|
||||
|
||||
vop_last_rate = common_info->vop_req_rate;
|
||||
common_info->vop_req_rate = target;
|
||||
|
||||
|
||||
@@ -274,8 +274,6 @@ struct dw_mipi_dsi2 {
|
||||
struct rockchip_drm_sub_dev sub_dev;
|
||||
|
||||
struct gpio_desc *te_gpio;
|
||||
bool user_split_mode;
|
||||
struct drm_property *user_split_mode_prop;
|
||||
};
|
||||
|
||||
static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host)
|
||||
@@ -1218,21 +1216,6 @@ static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2,
|
||||
struct drm_connector *connector)
|
||||
{
|
||||
struct device *dev = dsi2->dev;
|
||||
struct drm_property *prop;
|
||||
int ret;
|
||||
|
||||
prop = drm_property_create_bool(dsi2->drm_dev, DRM_MODE_PROP_IMMUTABLE,
|
||||
"USER_SPLIT_MODE");
|
||||
if (!prop) {
|
||||
ret = -EINVAL;
|
||||
DRM_DEV_ERROR(dev, "create user split mode prop failed\n");
|
||||
goto connector_cleanup;
|
||||
}
|
||||
|
||||
dsi2->user_split_mode_prop = prop;
|
||||
drm_object_attach_property(&connector->base,
|
||||
dsi2->user_split_mode_prop,
|
||||
dsi2->user_split_mode ? 1 : 0);
|
||||
|
||||
dsi2->sub_dev.connector = connector;
|
||||
dsi2->sub_dev.of_node = dev->of_node;
|
||||
@@ -1240,11 +1223,6 @@ static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2,
|
||||
rockchip_drm_register_sub_dev(&dsi2->sub_dev);
|
||||
|
||||
return 0;
|
||||
|
||||
connector_cleanup:
|
||||
connector->funcs->destroy(connector);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dw_mipi_dsi2_bind(struct device *dev, struct device *master,
|
||||
@@ -1562,7 +1540,6 @@ static int dw_mipi_dsi2_probe(struct platform_device *pdev)
|
||||
dsi2->id = id;
|
||||
dsi2->pdata = of_device_get_match_data(dev);
|
||||
platform_set_drvdata(pdev, dsi2);
|
||||
dsi2->user_split_mode = device_property_read_bool(dev, "user-split-mode");
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
regs = devm_ioremap_resource(dev, res);
|
||||
|
||||
@@ -201,7 +201,6 @@ struct rockchip_hdmi {
|
||||
u8 id;
|
||||
bool hpd_stat;
|
||||
bool is_hdmi_qp;
|
||||
bool user_split_mode;
|
||||
|
||||
unsigned long bus_format;
|
||||
unsigned long output_bus_format;
|
||||
@@ -219,7 +218,6 @@ struct rockchip_hdmi {
|
||||
struct drm_property *next_hdr_sink_data_property;
|
||||
struct drm_property *output_hdmi_dvi;
|
||||
struct drm_property *output_type_capacity;
|
||||
struct drm_property *user_split_mode_prop;
|
||||
struct drm_property *allm_capacity;
|
||||
struct drm_property *allm_enable;
|
||||
|
||||
@@ -2730,14 +2728,6 @@ dw_hdmi_rockchip_attach_properties(struct drm_connector *connector,
|
||||
drm_object_attach_property(&connector->base, prop, 0);
|
||||
}
|
||||
|
||||
prop = drm_property_create_bool(connector->dev, DRM_MODE_PROP_IMMUTABLE,
|
||||
"USER_SPLIT_MODE");
|
||||
if (prop) {
|
||||
hdmi->user_split_mode_prop = prop;
|
||||
drm_object_attach_property(&connector->base, prop,
|
||||
hdmi->user_split_mode ? 1 : 0);
|
||||
}
|
||||
|
||||
prop = drm_property_create_bool(connector->dev, 0, "allm_capacity");
|
||||
if (prop) {
|
||||
hdmi->allm_capacity = prop;
|
||||
@@ -2854,12 +2844,6 @@ dw_hdmi_rockchip_destroy_properties(struct drm_connector *connector,
|
||||
hdmi->output_type_capacity = NULL;
|
||||
}
|
||||
|
||||
if (hdmi->user_split_mode_prop) {
|
||||
drm_property_destroy(connector->dev,
|
||||
hdmi->user_split_mode_prop);
|
||||
hdmi->user_split_mode_prop = NULL;
|
||||
}
|
||||
|
||||
if (hdmi->allm_capacity) {
|
||||
drm_property_destroy(connector->dev,
|
||||
hdmi->allm_capacity);
|
||||
@@ -3001,9 +2985,6 @@ dw_hdmi_rockchip_get_property(struct drm_connector *connector,
|
||||
else
|
||||
*val = dw_hdmi_qp_get_output_type_cap(hdmi->hdmi_qp);
|
||||
return 0;
|
||||
} else if (property == hdmi->user_split_mode_prop) {
|
||||
*val = hdmi->user_split_mode;
|
||||
return 0;
|
||||
} else if (property == hdmi->allm_capacity) {
|
||||
*val = !!(hdmi->add_func & SUPPORT_HDMI_ALLM);
|
||||
return 0;
|
||||
@@ -3516,12 +3497,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
|
||||
if (!secondary->plat_data->first_screen)
|
||||
plat_data->first_screen = true;
|
||||
}
|
||||
|
||||
if (device_property_read_bool(dev, "user-split-mode") ||
|
||||
device_property_read_bool(secondary->dev, "user-split-mode")) {
|
||||
hdmi->user_split_mode = true;
|
||||
secondary->user_split_mode = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (!plat_data->first_screen) {
|
||||
|
||||
@@ -1297,6 +1297,12 @@ static void rockchip_drm_debugfs_init(struct drm_minor *minor)
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct drm_prop_enum_list split_area[] = {
|
||||
{ ROCKCHIP_DRM_SPLIT_UNSET, "UNSET" },
|
||||
{ ROCKCHIP_DRM_SPLIT_LEFT_SIDE, "LEFT" },
|
||||
{ ROCKCHIP_DRM_SPLIT_RIGHT_SIDE, "RIGHT" },
|
||||
};
|
||||
|
||||
static int rockchip_drm_create_properties(struct drm_device *dev)
|
||||
{
|
||||
struct drm_property *prop;
|
||||
@@ -1332,6 +1338,11 @@ static int rockchip_drm_create_properties(struct drm_device *dev)
|
||||
return -ENOMEM;
|
||||
private->connector_id_prop = prop;
|
||||
|
||||
prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "SPLIT_AREA",
|
||||
split_area,
|
||||
ARRAY_SIZE(split_area));
|
||||
private->split_area_prop = prop;
|
||||
|
||||
prop = drm_property_create_object(dev,
|
||||
DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE,
|
||||
"SOC_ID", DRM_MODE_OBJECT_CRTC);
|
||||
|
||||
@@ -110,6 +110,12 @@ enum rockchip_color_bar_mode {
|
||||
ROCKCHIP_COLOR_BAR_VERTICAL = 2,
|
||||
};
|
||||
|
||||
enum rockchip_drm_split_area {
|
||||
ROCKCHIP_DRM_SPLIT_UNSET = 0,
|
||||
ROCKCHIP_DRM_SPLIT_LEFT_SIDE = 1,
|
||||
ROCKCHIP_DRM_SPLIT_RIGHT_SIDE = 2,
|
||||
};
|
||||
|
||||
struct rockchip_drm_sub_dev {
|
||||
struct list_head list;
|
||||
struct drm_connector *connector;
|
||||
@@ -260,6 +266,7 @@ struct rockchip_crtc_state {
|
||||
int afbdc_win_yoffset;
|
||||
int dsp_layer_sel;
|
||||
u32 output_if;
|
||||
u32 output_if_left_panel;
|
||||
u32 bus_format;
|
||||
u32 bus_flags;
|
||||
int yuv_overlay;
|
||||
@@ -433,7 +440,7 @@ struct next_hdr_sink_data {
|
||||
* @wait_vact_end: wait the last active line.
|
||||
*/
|
||||
struct rockchip_crtc_funcs {
|
||||
int (*loader_protect)(struct drm_crtc *crtc, bool on);
|
||||
int (*loader_protect)(struct drm_crtc *crtc, bool on, void *data);
|
||||
int (*enable_vblank)(struct drm_crtc *crtc);
|
||||
void (*disable_vblank)(struct drm_crtc *crtc);
|
||||
size_t (*bandwidth)(struct drm_crtc *crtc,
|
||||
@@ -498,6 +505,7 @@ struct rockchip_drm_private {
|
||||
|
||||
/* private connector prop */
|
||||
struct drm_property *connector_id_prop;
|
||||
struct drm_property *split_area_prop;
|
||||
|
||||
const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
|
||||
|
||||
|
||||
@@ -164,6 +164,7 @@ static int rockchip_drm_bandwidth_atomic_check(struct drm_device *dev,
|
||||
vop_bw_info->line_bw_mbyte = 0;
|
||||
vop_bw_info->frame_bw_mbyte = 0;
|
||||
vop_bw_info->plane_num = 0;
|
||||
vop_bw_info->plane_num_4k = 0;
|
||||
|
||||
for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
|
||||
funcs = priv->crtc_funcs[drm_crtc_index(crtc)];
|
||||
|
||||
@@ -376,6 +376,69 @@ get_framebuffer_by_node(struct drm_device *drm_dev, struct device_node *node)
|
||||
return rockchip_drm_logo_fb_alloc(drm_dev, &mode_cmd, private->logo);
|
||||
}
|
||||
|
||||
static void of_parse_post_csc_info(struct device_node *route, struct rockchip_drm_mode_set *set)
|
||||
{
|
||||
int val;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,enable", &val))
|
||||
set->csc.csc_enable = val;
|
||||
else
|
||||
set->csc.csc_enable = 0;
|
||||
|
||||
if (!set->csc.csc_enable)
|
||||
return;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,hue", &val))
|
||||
set->csc.hue = val;
|
||||
else
|
||||
set->csc.hue = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,saturation", &val))
|
||||
set->csc.saturation = val;
|
||||
else
|
||||
set->csc.saturation = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,contrast", &val))
|
||||
set->csc.contrast = val;
|
||||
else
|
||||
set->csc.contrast = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,brightness", &val))
|
||||
set->csc.brightness = val;
|
||||
else
|
||||
set->csc.brightness = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,r-gain", &val))
|
||||
set->csc.r_gain = val;
|
||||
else
|
||||
set->csc.r_gain = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,g-gain", &val))
|
||||
set->csc.g_gain = val;
|
||||
else
|
||||
set->csc.g_gain = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,b-gain", &val))
|
||||
set->csc.b_gain = val;
|
||||
else
|
||||
set->csc.b_gain = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,r-offset", &val))
|
||||
set->csc.r_offset = val;
|
||||
else
|
||||
set->csc.r_offset = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,g-offset", &val))
|
||||
set->csc.g_offset = val;
|
||||
else
|
||||
set->csc.g_offset = 256;
|
||||
|
||||
if (!of_property_read_u32(route, "post-csc,b-offset", &val))
|
||||
set->csc.b_offset = val;
|
||||
else
|
||||
set->csc.b_offset = 256;
|
||||
}
|
||||
|
||||
static struct rockchip_drm_mode_set *
|
||||
of_parse_display_resource(struct drm_device *drm_dev, struct device_node *route)
|
||||
{
|
||||
@@ -470,6 +533,8 @@ of_parse_display_resource(struct drm_device *drm_dev, struct device_node *route)
|
||||
else
|
||||
set->hue = 50;
|
||||
|
||||
of_parse_post_csc_info(route, set);
|
||||
|
||||
set->force_output = of_property_read_bool(route, "force-output");
|
||||
|
||||
if (!of_property_read_u32(route, "cubic_lut,offset", &val)) {
|
||||
@@ -746,7 +811,7 @@ static int setup_initial_state(struct drm_device *drm_dev,
|
||||
|
||||
if (priv->crtc_funcs[pipe] &&
|
||||
priv->crtc_funcs[pipe]->loader_protect)
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, true);
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, true, &set->csc);
|
||||
}
|
||||
|
||||
if (!set->fb) {
|
||||
@@ -798,7 +863,7 @@ static int setup_initial_state(struct drm_device *drm_dev,
|
||||
|
||||
error_crtc:
|
||||
if (priv->crtc_funcs[pipe] && priv->crtc_funcs[pipe]->loader_protect)
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, false);
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, false, NULL);
|
||||
error_conn:
|
||||
if (set->sub_dev->loader_protect)
|
||||
set->sub_dev->loader_protect(conn_state->best_encoder, false);
|
||||
@@ -994,11 +1059,12 @@ void rockchip_drm_show_logo(struct drm_device *drm_dev)
|
||||
unset);
|
||||
if (priv->crtc_funcs[pipe] &&
|
||||
priv->crtc_funcs[pipe]->loader_protect)
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, true);
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, true,
|
||||
&set->csc);
|
||||
priv->crtc_funcs[pipe]->crtc_close(crtc);
|
||||
if (priv->crtc_funcs[pipe] &&
|
||||
priv->crtc_funcs[pipe]->loader_protect)
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, false);
|
||||
priv->crtc_funcs[pipe]->loader_protect(crtc, false, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -7,12 +7,15 @@
|
||||
#ifndef ROCKCHIP_DRM_LOGO_H
|
||||
#define ROCKCHIP_DRM_LOGO_H
|
||||
|
||||
#include "rockchip_drm_vop.h"
|
||||
|
||||
struct rockchip_drm_mode_set {
|
||||
struct list_head head;
|
||||
struct drm_framebuffer *fb;
|
||||
struct rockchip_drm_sub_dev *sub_dev;
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_display_mode *mode;
|
||||
struct post_csc csc;
|
||||
int clock;
|
||||
int hdisplay;
|
||||
int vdisplay;
|
||||
|
||||
@@ -2639,7 +2639,7 @@ static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
|
||||
spin_unlock_irqrestore(&drm->event_lock, flags);
|
||||
}
|
||||
|
||||
static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
|
||||
static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
|
||||
{
|
||||
struct rockchip_drm_private *private = crtc->dev->dev_private;
|
||||
struct vop *vop = to_vop(crtc);
|
||||
|
||||
@@ -31,11 +31,15 @@
|
||||
#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
|
||||
#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
|
||||
|
||||
/* register one connector */
|
||||
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
|
||||
/* register one connector */
|
||||
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
|
||||
#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
|
||||
/* MIPI DSI DataStream(cmd) mode on rk3588 */
|
||||
#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
|
||||
/* register two connector */
|
||||
#define ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE BIT(4)
|
||||
|
||||
#define AFBDC_FMT_RGB565 0x0
|
||||
#define AFBDC_FMT_U8U8U8U8 0x5
|
||||
|
||||
@@ -4362,8 +4362,11 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
|
||||
if (vp->output_if & VOP_OUTPUT_IF_eDP0)
|
||||
VOP_GRF_SET(vop2, grf, grf_edp0_en, 0);
|
||||
|
||||
if (vp->output_if & VOP_OUTPUT_IF_eDP1)
|
||||
if (vp->output_if & VOP_OUTPUT_IF_eDP1) {
|
||||
VOP_GRF_SET(vop2, grf, grf_edp1_en, 0);
|
||||
if (dual_channel)
|
||||
VOP_CTRL_SET(vop2, edp_dual_en, 0);
|
||||
}
|
||||
|
||||
if (vp->output_if & VOP_OUTPUT_IF_HDMI0) {
|
||||
VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 0);
|
||||
@@ -4373,8 +4376,16 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
|
||||
if (vp->output_if & VOP_OUTPUT_IF_HDMI1) {
|
||||
VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 0);
|
||||
VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 0);
|
||||
if (dual_channel)
|
||||
VOP_CTRL_SET(vop2, hdmi_dual_en, 0);
|
||||
}
|
||||
|
||||
if ((vcstate->output_if & VOP_OUTPUT_IF_DP1) && dual_channel)
|
||||
VOP_CTRL_SET(vop2, dp_dual_en, 0);
|
||||
|
||||
if ((vcstate->output_if & VOP_OUTPUT_IF_MIPI1) && dual_channel)
|
||||
VOP_CTRL_SET(vop2, mipi_dual_en, 0);
|
||||
|
||||
VOP_MODULE_SET(vop2, vp, dual_channel_en, 0);
|
||||
VOP_MODULE_SET(vop2, vp, dual_channel_swap, 0);
|
||||
|
||||
@@ -5878,7 +5889,58 @@ static void vop2_crtc_disable_line_flag_event(struct drm_crtc *crtc)
|
||||
spin_unlock_irqrestore(&vop2->irq_lock, flags);
|
||||
}
|
||||
|
||||
static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on)
|
||||
static int vop2_crtc_get_inital_acm_info(struct drm_crtc *crtc)
|
||||
{
|
||||
struct vop2_video_port *vp = to_vop2_video_port(crtc);
|
||||
struct vop2 *vop2 = vp->vop2;
|
||||
struct post_acm *acm = &vp->acm_info;
|
||||
s16 *lut_y;
|
||||
s16 *lut_h;
|
||||
s16 *lut_s;
|
||||
u32 value;
|
||||
int i;
|
||||
|
||||
value = readl(vop2->acm_regs + RK3528_ACM_CTRL);
|
||||
acm->acm_enable = value & 0x1;
|
||||
value = readl(vop2->acm_regs + RK3528_ACM_DELTA_RANGE);
|
||||
acm->y_gain = value & 0x3ff;
|
||||
acm->h_gain = (value >> 10) & 0x3ff;
|
||||
acm->s_gain = (value >> 20) & 0x3ff;
|
||||
|
||||
lut_y = &acm->gain_lut_hy[0];
|
||||
lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
|
||||
lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
|
||||
for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
|
||||
value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
|
||||
lut_y[i] = value & 0xff;
|
||||
lut_h[i] = (value >> 8) & 0xff;
|
||||
lut_s[i] = (value >> 16) & 0xff;
|
||||
}
|
||||
|
||||
lut_y = &acm->gain_lut_hs[0];
|
||||
lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
|
||||
lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
|
||||
for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
|
||||
value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
|
||||
lut_y[i] = value & 0xff;
|
||||
lut_h[i] = (value >> 8) & 0xff;
|
||||
lut_s[i] = (value >> 16) & 0xff;
|
||||
}
|
||||
|
||||
lut_y = &acm->delta_lut_h[0];
|
||||
lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
|
||||
lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
|
||||
for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
|
||||
value = readl(vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
|
||||
lut_y[i] = value & 0x3ff;
|
||||
lut_h[i] = (value >> 12) & 0xff;
|
||||
lut_s[i] = (value >> 20) & 0x3ff;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
|
||||
{
|
||||
struct vop2_video_port *vp = to_vop2_video_port(crtc);
|
||||
struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
|
||||
@@ -5942,6 +6004,12 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on)
|
||||
ext_pll->vp_mask |= BIT(vp->id);
|
||||
}
|
||||
drm_crtc_vblank_on(crtc);
|
||||
if (is_vop3(vop2)) {
|
||||
if (vp_data->feature & (VOP_FEATURE_POST_ACM))
|
||||
vop2_crtc_get_inital_acm_info(crtc);
|
||||
if (data && (vp_data->feature & VOP_FEATURE_POST_CSC))
|
||||
memcpy(&vp->csc_info, data, sizeof(struct post_csc));
|
||||
}
|
||||
if (private->cubic_lut[vp->id].enable) {
|
||||
dma_addr_t cubic_lut_mst;
|
||||
struct loader_cubic_lut *cubic_lut = &private->cubic_lut[vp->id];
|
||||
@@ -6350,9 +6418,9 @@ static size_t vop2_plane_line_bandwidth(struct drm_plane_state *pstate)
|
||||
|
||||
bandwidth = bandwidth * src_width / dst_width;
|
||||
bandwidth = bandwidth * src_height / dst_height;
|
||||
if (vskiplines == 2)
|
||||
if (vskiplines == 2 && vpstate->afbc_en == 0)
|
||||
bandwidth /= 2;
|
||||
else if (vskiplines == 4)
|
||||
else if (vskiplines == 4 && vpstate->afbc_en == 0)
|
||||
bandwidth /= 4;
|
||||
|
||||
return bandwidth;
|
||||
@@ -6446,9 +6514,12 @@ static size_t vop2_crtc_bandwidth(struct drm_crtc *crtc,
|
||||
|
||||
act_w = drm_rect_width(&pstate->src) >> 16;
|
||||
act_h = drm_rect_height(&pstate->src) >> 16;
|
||||
if (pstate->fb->format->is_yuv && (act_w >= 3840 || act_h >= 3840))
|
||||
vop_bw_info->plane_num_4k++;
|
||||
|
||||
bpp = rockchip_drm_get_bpp(pstate->fb->format);
|
||||
|
||||
vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000;
|
||||
vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000 / afbc_fac;
|
||||
}
|
||||
|
||||
sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop2_bandwidth_cmp, NULL);
|
||||
@@ -7257,6 +7328,11 @@ static void vop2_crtc_enable_dsc(struct drm_crtc *crtc, struct drm_crtc_state *o
|
||||
dsc->enabled = true;
|
||||
}
|
||||
|
||||
static inline bool vop2_mark_as_left_panel(struct rockchip_crtc_state *vcstate, u32 output_if)
|
||||
{
|
||||
return vcstate->output_if_left_panel & output_if;
|
||||
}
|
||||
|
||||
static void vop2_setup_dual_channel_if(struct drm_crtc *crtc)
|
||||
{
|
||||
struct vop2_video_port *vp = to_vop2_video_port(crtc);
|
||||
@@ -7267,13 +7343,17 @@ static void vop2_setup_dual_channel_if(struct drm_crtc *crtc)
|
||||
if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
|
||||
VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1);
|
||||
|
||||
if (vcstate->output_if & VOP_OUTPUT_IF_DP1)
|
||||
if (vcstate->output_if & VOP_OUTPUT_IF_DP1 &&
|
||||
!vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_DP1))
|
||||
VOP_CTRL_SET(vop2, dp_dual_en, 1);
|
||||
else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1)
|
||||
else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1 &&
|
||||
!vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_eDP1))
|
||||
VOP_CTRL_SET(vop2, edp_dual_en, 1);
|
||||
else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)
|
||||
else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1 &&
|
||||
!vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_HDMI1))
|
||||
VOP_CTRL_SET(vop2, hdmi_dual_en, 1);
|
||||
else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1)
|
||||
else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1 &&
|
||||
!vop2_mark_as_left_panel(vcstate, VOP_OUTPUT_IF_MIPI1))
|
||||
VOP_CTRL_SET(vop2, mipi_dual_en, 1);
|
||||
}
|
||||
|
||||
@@ -7489,9 +7569,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta
|
||||
vop2_set_system_status(vop2);
|
||||
|
||||
vop2_lock(vop2);
|
||||
DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x) for vp%d dclk: %d\n",
|
||||
DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x, flag:0x%x) for vp%d dclk: %d\n",
|
||||
hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p",
|
||||
vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if,
|
||||
vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if, vcstate->output_flags,
|
||||
vp->id, adjusted_mode->crtc_clock * 1000);
|
||||
|
||||
if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
|
||||
@@ -7503,6 +7583,9 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta
|
||||
vop2->active_vp_mask |= BIT(splice_vp->id);
|
||||
}
|
||||
|
||||
if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE)
|
||||
vcstate->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
|
||||
|
||||
if (vcstate->dsc_enable) {
|
||||
int k = 1;
|
||||
|
||||
|
||||
@@ -606,8 +606,7 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(vts >> 8) & 0x3f);
|
||||
ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
|
||||
vts & 0xff);
|
||||
if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
|
||||
gc2093_modify_fps_info(gc2093);
|
||||
gc2093_modify_fps_info(gc2093);
|
||||
dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_HFLIP:
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1040,8 +1040,7 @@ static int sc031gs_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc031gs->cur_mode->height);
|
||||
if (!ret)
|
||||
sc031gs->cur_vts = ctrl->val + sc031gs->cur_mode->height;
|
||||
if (sc031gs->cur_vts != sc031gs->cur_mode->vts_def)
|
||||
sc031gs_modify_fps_info(sc031gs);
|
||||
sc031gs_modify_fps_info(sc031gs);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc031gs_enable_test_pattern(sc031gs, ctrl->val);
|
||||
|
||||
@@ -1021,8 +1021,7 @@ static int sc035gs_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc035gs->cur_mode->height);
|
||||
if (!ret)
|
||||
sc035gs->cur_vts = ctrl->val + sc035gs->cur_mode->height;
|
||||
if (sc035gs->cur_vts != sc035gs->cur_mode->vts_def)
|
||||
sc035gs_modify_fps_info(sc035gs);
|
||||
sc035gs_modify_fps_info(sc035gs);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc035gs_enable_test_pattern(sc035gs, ctrl->val);
|
||||
|
||||
@@ -1136,8 +1136,7 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc132gs->cur_mode->height);
|
||||
if (!ret)
|
||||
sc132gs->cur_vts = ctrl->val + sc132gs->cur_mode->height;
|
||||
if (sc132gs->cur_vts != sc132gs->cur_mode->vts_def)
|
||||
sc132gs_modify_fps_info(sc132gs);
|
||||
sc132gs_modify_fps_info(sc132gs);
|
||||
break;
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
|
||||
@@ -1733,8 +1733,7 @@ static int sc200ai_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
& 0xff);
|
||||
if (!ret)
|
||||
sc200ai->cur_vts = ctrl->val + sc200ai->cur_mode->height;
|
||||
if (sc200ai->cur_vts != sc200ai->cur_mode->vts_def)
|
||||
sc200ai_modify_fps_info(sc200ai);
|
||||
sc200ai_modify_fps_info(sc200ai);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc200ai_enable_test_pattern(sc200ai, ctrl->val);
|
||||
|
||||
@@ -408,8 +408,7 @@ static int sc210iot_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(ctrl->val + sc210iot->cur_mode->height) & 0xff);
|
||||
if (!ret)
|
||||
sc210iot->cur_vts = ctrl->val + sc210iot->cur_mode->height;
|
||||
if (sc210iot->cur_vts != sc210iot->cur_mode->vts_def)
|
||||
sc210iot_modify_fps_info(sc210iot);
|
||||
sc210iot_modify_fps_info(sc210iot);
|
||||
break;
|
||||
case V4L2_CID_HFLIP:
|
||||
regmap_update_bits(sc210iot->regmap, SC210IOT_REG_MIRROR_FLIP,
|
||||
|
||||
@@ -1205,8 +1205,7 @@ static int sc2232_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc2232->cur_mode->height);
|
||||
if (!ret)
|
||||
sc2232->cur_vts = ctrl->val + sc2232->cur_mode->height;
|
||||
if (sc2232->cur_vts != sc2232->cur_mode->vts_def)
|
||||
sc2232_modify_fps_info(sc2232);
|
||||
sc2232_modify_fps_info(sc2232);
|
||||
dev_dbg(&client->dev, "set vblank 0x%x\n",
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
@@ -970,8 +970,7 @@ static int sc2239_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc2239->cur_mode->height);
|
||||
if (!ret)
|
||||
sc2239->cur_vts = ctrl->val + sc2239->cur_mode->height;
|
||||
if (sc2239->cur_vts != sc2239->cur_mode->vts_def)
|
||||
sc2239_modify_fps_info(sc2239);
|
||||
sc2239_modify_fps_info(sc2239);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc2239_enable_test_pattern(sc2239, ctrl->val);
|
||||
|
||||
@@ -1243,8 +1243,7 @@ static int sc223a_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(ctrl->val + sc223a->cur_mode->height)
|
||||
& 0xff);
|
||||
sc223a->cur_vts = ctrl->val + sc223a->cur_mode->height;
|
||||
if (sc223a->cur_vts != sc223a->cur_mode->vts_def)
|
||||
sc223a_modify_fps_info(sc223a);
|
||||
sc223a_modify_fps_info(sc223a);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc223a_enable_test_pattern(sc223a, ctrl->val);
|
||||
|
||||
@@ -1458,8 +1458,7 @@ static int sc230ai_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(ctrl->val + sc230ai->cur_mode->height)
|
||||
& 0xff);
|
||||
sc230ai->cur_vts = ctrl->val + sc230ai->cur_mode->height;
|
||||
if (sc230ai->cur_vts != sc230ai->cur_mode->vts_def)
|
||||
sc230ai_modify_fps_info(sc230ai);
|
||||
sc230ai_modify_fps_info(sc230ai);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc230ai_enable_test_pattern(sc230ai, ctrl->val);
|
||||
|
||||
@@ -1639,8 +1639,7 @@ static int sc2310_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc2310->cur_mode->height);
|
||||
if (!ret)
|
||||
sc2310->cur_vts = ctrl->val + sc2310->cur_mode->height;
|
||||
if (sc2310->cur_vts != sc2310->cur_mode->vts_def)
|
||||
sc2310_modify_fps_info(sc2310);
|
||||
sc2310_modify_fps_info(sc2310);
|
||||
dev_dbg(&client->dev, "set vblank 0x%x\n",
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
@@ -1941,8 +1941,7 @@ static int SC301IOT_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
& 0xff);
|
||||
if (!ret)
|
||||
SC301IOT->cur_vts = ctrl->val + SC301IOT->cur_mode->height;
|
||||
if (SC301IOT->cur_vts != SC301IOT->cur_mode->vts_def)
|
||||
SC301IOT_modify_fps_info(SC301IOT);
|
||||
SC301IOT_modify_fps_info(SC301IOT);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = SC301IOT_enable_test_pattern(SC301IOT, ctrl->val);
|
||||
|
||||
@@ -1371,8 +1371,7 @@ static int sc3336_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(ctrl->val + sc3336->cur_mode->height)
|
||||
& 0xff);
|
||||
sc3336->cur_vts = ctrl->val + sc3336->cur_mode->height;
|
||||
if (sc3336->cur_vts != sc3336->cur_mode->vts_def)
|
||||
sc3336_modify_fps_info(sc3336);
|
||||
sc3336_modify_fps_info(sc3336);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc3336_enable_test_pattern(sc3336, ctrl->val);
|
||||
|
||||
@@ -1190,8 +1190,7 @@ static int sc3338_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(ctrl->val + sc3338->cur_mode->height)
|
||||
& 0xff);
|
||||
sc3338->cur_vts = ctrl->val + sc3338->cur_mode->height;
|
||||
if (sc3338->cur_vts != sc3338->cur_mode->vts_def)
|
||||
sc3338_modify_fps_info(sc3338);
|
||||
sc3338_modify_fps_info(sc3338);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc3338_enable_test_pattern(sc3338, ctrl->val);
|
||||
|
||||
@@ -1320,8 +1320,7 @@ static int sc401ai_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
& 0xff);
|
||||
if (!ret)
|
||||
sc401ai->cur_vts = ctrl->val + sc401ai->cur_mode->height;
|
||||
if (sc401ai->cur_vts != sc401ai->cur_mode->vts_def)
|
||||
sc401ai_modify_fps_info(sc401ai);
|
||||
sc401ai_modify_fps_info(sc401ai);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc401ai_enable_test_pattern(sc401ai, ctrl->val);
|
||||
|
||||
@@ -2398,8 +2398,7 @@ static int sc4210_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
SC4210_REG_VALUE_08BIT,
|
||||
vts & 0xff);
|
||||
sc4210->cur_vts = ctrl->val + sc4210->cur_mode->height;
|
||||
if (sc4210->cur_vts != sc4210->cur_mode->vts_def)
|
||||
sc4210_modify_fps_info(sc4210);
|
||||
sc4210_modify_fps_info(sc4210);
|
||||
dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_HFLIP:
|
||||
|
||||
@@ -2470,8 +2470,7 @@ static int sc4238_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc4238->cur_mode->height);
|
||||
if (ret == 0)
|
||||
sc4238->cur_vts = ctrl->val + sc4238->cur_mode->height;
|
||||
if (sc4238->cur_vts != sc4238->cur_mode->vts_def)
|
||||
sc4238_modify_fps_info(sc4238);
|
||||
sc4238_modify_fps_info(sc4238);
|
||||
dev_dbg(&client->dev, "set vblank 0x%x\n",
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
@@ -1191,8 +1191,7 @@ static int sc430cs_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
& 0xff);
|
||||
if (!ret)
|
||||
sc430cs->cur_vts = ctrl->val + sc430cs->cur_mode->height;
|
||||
if (sc430cs->cur_vts != sc430cs->cur_mode->vts_def)
|
||||
sc430cs_modify_fps_info(sc430cs);
|
||||
sc430cs_modify_fps_info(sc430cs);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc430cs_enable_test_pattern(sc430cs, ctrl->val);
|
||||
|
||||
@@ -1188,8 +1188,7 @@ static int sc4336_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
(ctrl->val + sc4336->cur_mode->height)
|
||||
& 0xff);
|
||||
sc4336->cur_vts = ctrl->val + sc4336->cur_mode->height;
|
||||
if (sc4336->cur_vts != sc4336->cur_mode->vts_def)
|
||||
sc4336_modify_fps_info(sc4336);
|
||||
sc4336_modify_fps_info(sc4336);
|
||||
break;
|
||||
case V4L2_CID_TEST_PATTERN:
|
||||
ret = sc4336_enable_test_pattern(sc4336, ctrl->val);
|
||||
|
||||
@@ -1478,8 +1478,7 @@ static int sc500ai_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
vts & 0xff);
|
||||
if (!ret)
|
||||
sc500ai->cur_vts = vts;
|
||||
if (sc500ai->cur_vts != sc500ai->cur_mode->vts_def)
|
||||
sc500ai_modify_fps_info(sc500ai);
|
||||
sc500ai_modify_fps_info(sc500ai);
|
||||
break;
|
||||
case V4L2_CID_HFLIP:
|
||||
ret = sc500ai_read_reg(sc500ai->client, SC500AI_FLIP_MIRROR_REG,
|
||||
|
||||
@@ -1041,8 +1041,7 @@ static int sc501ai_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
SC501AI_REG_VALUE_08BIT,
|
||||
vts & 0xff);
|
||||
sc501ai->cur_vts = vts;
|
||||
if (sc501ai->cur_vts != sc501ai->cur_mode->vts_def)
|
||||
sc501ai_modify_fps_info(sc501ai);
|
||||
sc501ai_modify_fps_info(sc501ai);
|
||||
break;
|
||||
case V4L2_CID_HFLIP:
|
||||
ret = sc501ai_read_reg(sc501ai->client, SC501AI_FLIP_MIRROR_REG,
|
||||
|
||||
@@ -1706,8 +1706,7 @@ static int sc530ai_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
vts & 0xff);
|
||||
if (!ret)
|
||||
sc530ai->cur_vts = vts;
|
||||
if (sc530ai->cur_vts != sc530ai->cur_mode->vts_def)
|
||||
sc530ai_modify_fps_info(sc530ai);
|
||||
sc530ai_modify_fps_info(sc530ai);
|
||||
dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
|
||||
break;
|
||||
case V4L2_CID_HFLIP:
|
||||
|
||||
@@ -1399,8 +1399,7 @@ static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl)
|
||||
ctrl->val + sc850sl->cur_mode->height);
|
||||
if (!ret)
|
||||
sc850sl->cur_vts = ctrl->val + sc850sl->cur_mode->height;
|
||||
if (sc850sl->cur_vts != sc850sl->cur_mode->vts_def)
|
||||
sc850sl_modify_fps_info(sc850sl);
|
||||
sc850sl_modify_fps_info(sc850sl);
|
||||
dev_dbg(&client->dev, "set vblank 0x%x\n",
|
||||
ctrl->val);
|
||||
break;
|
||||
|
||||
@@ -789,21 +789,22 @@ static void update_mi(struct rkisp_stream *stream)
|
||||
if (dev->hw_dev->is_unite) {
|
||||
u32 mult = stream->id != RKISP_STREAM_FBC ? 1 :
|
||||
(stream->out_isp_fmt.write_format ? 32 : 24);
|
||||
u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2;
|
||||
|
||||
reg = stream->config->mi.y_base_ad_init;
|
||||
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
|
||||
val += ((stream->out_fmt.width / 2) & ~0xf);
|
||||
val += ((stream->out_fmt.width / div) & ~0xf);
|
||||
rkisp_next_write(dev, reg, val, false);
|
||||
|
||||
reg = stream->config->mi.cb_base_ad_init;
|
||||
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
|
||||
val += ((stream->out_fmt.width / 2) & ~0xf) * mult;
|
||||
val += ((stream->out_fmt.width / div) & ~0xf) * mult;
|
||||
rkisp_next_write(dev, reg, val, false);
|
||||
|
||||
if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP) {
|
||||
reg = stream->config->mi.cr_base_ad_init;
|
||||
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
|
||||
val += ((stream->out_fmt.width / 2) & ~0xf);
|
||||
val += ((stream->out_fmt.width / div) & ~0xf);
|
||||
rkisp_next_write(dev, reg, val, false);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -976,6 +976,8 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
|
||||
rkisp_update_sensor_info(isp_dev) >= 0)
|
||||
_set_pipeline_default_fmt(isp_dev, false);
|
||||
|
||||
if (isp_dev->hw_dev->is_assigned_clk)
|
||||
rkisp_clk_dbg = true;
|
||||
isp_dev->cap_dev.wait_line = rkisp_wait_line;
|
||||
isp_dev->cap_dev.wrap_line = rkisp_wrap_line;
|
||||
isp_dev->is_rdbk_auto = rkisp_rdbk_auto;
|
||||
|
||||
@@ -740,10 +740,12 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev)
|
||||
}
|
||||
}
|
||||
|
||||
rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL;
|
||||
rkisp_set_clk_rate(dev->clks[0], rate);
|
||||
if (dev->is_unite)
|
||||
rkisp_set_clk_rate(dev->clks[5], rate);
|
||||
if (!dev->is_assigned_clk) {
|
||||
rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL;
|
||||
rkisp_set_clk_rate(dev->clks[0], rate);
|
||||
if (dev->is_unite)
|
||||
rkisp_set_clk_rate(dev->clks[5], rate);
|
||||
}
|
||||
rkisp_soft_reset(dev, false);
|
||||
isp_config_clk(dev, true);
|
||||
return 0;
|
||||
@@ -802,6 +804,7 @@ static int rkisp_hw_probe(struct platform_device *pdev)
|
||||
struct resource *res;
|
||||
int i, ret;
|
||||
bool is_mem_reserved = true;
|
||||
u32 clk_rate = 0;
|
||||
|
||||
match = of_match_node(rkisp_hw_of_match, node);
|
||||
if (IS_ERR(match))
|
||||
@@ -895,6 +898,11 @@ static int rkisp_hw_probe(struct platform_device *pdev)
|
||||
hw_dev->clk_rate_tbl = match_data->clk_rate_tbl;
|
||||
hw_dev->num_clk_rate_tbl = match_data->num_clk_rate_tbl;
|
||||
|
||||
hw_dev->is_assigned_clk = false;
|
||||
ret = of_property_read_u32(node, "assigned-clock-rates", &clk_rate);
|
||||
if (!ret && clk_rate)
|
||||
hw_dev->is_assigned_clk = true;
|
||||
|
||||
hw_dev->reset = devm_reset_control_array_get(dev, false, false);
|
||||
if (IS_ERR(hw_dev->reset)) {
|
||||
dev_dbg(dev, "failed to get reset\n");
|
||||
|
||||
@@ -104,6 +104,7 @@ struct rkisp_hw_dev {
|
||||
bool is_runing;
|
||||
bool is_frm_buf;
|
||||
bool is_dvfs;
|
||||
bool is_assigned_clk;
|
||||
};
|
||||
|
||||
int rkisp_register_irq(struct rkisp_hw_dev *dev);
|
||||
|
||||
@@ -732,6 +732,7 @@ run_next:
|
||||
is_upd = true;
|
||||
} else if (is_try) {
|
||||
rkisp_multi_overflow_hdl(dev, true);
|
||||
rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE);
|
||||
is_upd = true;
|
||||
}
|
||||
}
|
||||
@@ -2164,7 +2165,6 @@ static int rkisp_isp_start(struct rkisp_device *dev)
|
||||
|
||||
dev->isp_err_cnt = 0;
|
||||
dev->isp_isr_cnt = 0;
|
||||
dev->isp_state = ISP_START | ISP_FRAME_END;
|
||||
dev->irq_ends_mask |= ISP_FRAME_END;
|
||||
dev->irq_ends = 0;
|
||||
|
||||
@@ -2873,6 +2873,7 @@ static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
|
||||
rkisp_config_cif(isp_dev);
|
||||
rkisp_isp_start(isp_dev);
|
||||
rkisp_global_update_mi(isp_dev);
|
||||
isp_dev->isp_state = ISP_START | ISP_FRAME_END;
|
||||
rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -168,7 +168,7 @@ static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
|
||||
* It's impossible all 4 fixed phase won't be able to work.
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(degrees); i++) {
|
||||
degree = degrees[i] + priv->last_degree;
|
||||
degree = degrees[i] + priv->last_degree + 90;
|
||||
degree = degree % 360;
|
||||
clk_set_phase(priv->sample_clk, degree);
|
||||
if (!mmc_send_tuning(mmc, opcode, NULL))
|
||||
@@ -181,7 +181,7 @@ static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
|
||||
}
|
||||
|
||||
done:
|
||||
dev_info(host->dev, "Successfully tuned phase to %d\n", degrees[i]);
|
||||
dev_info(host->dev, "Successfully tuned phase to %d\n", degree);
|
||||
priv->last_degree = degree;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
|
||||
#define SPINAND_MFR_DOSILICON 0xE5
|
||||
|
||||
#define DOSICON_STATUS_ECC_MASK GENMASK(7, 4)
|
||||
#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4)
|
||||
#define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4)
|
||||
#define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
|
||||
#define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
|
||||
|
||||
@@ -70,12 +70,13 @@ static const struct mtd_ooblayout_ops js28u1gqscahg_ooblayout = {
|
||||
static int js28u1gqscahg_ecc_get_status(struct spinand_device *spinand,
|
||||
u8 status)
|
||||
{
|
||||
u8 eccsr = (status & GENMASK(6, 4)) >> 2;
|
||||
struct nand_device *nand = spinand_to_nand(spinand);
|
||||
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
|
||||
|
||||
if (eccsr <= 7)
|
||||
if (eccsr < 4)
|
||||
return eccsr;
|
||||
else if (eccsr == 12)
|
||||
return 8;
|
||||
else if (eccsr == 4)
|
||||
return nanddev_get_ecc_requirements(nand)->strength;
|
||||
else
|
||||
return -EBADMSG;
|
||||
}
|
||||
|
||||
@@ -69,12 +69,13 @@ static const struct mtd_ooblayout_ops tx25g01_ooblayout = {
|
||||
static int tx25g01_ecc_get_status(struct spinand_device *spinand,
|
||||
u8 status)
|
||||
{
|
||||
u8 eccsr = (status & GENMASK(6, 4)) >> 2;
|
||||
struct nand_device *nand = spinand_to_nand(spinand);
|
||||
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
|
||||
|
||||
if (eccsr <= 7)
|
||||
if (eccsr < 4)
|
||||
return eccsr;
|
||||
else if (eccsr == 12)
|
||||
return 8;
|
||||
else if (eccsr == 4)
|
||||
return nanddev_get_ecc_requirements(nand)->strength;
|
||||
else
|
||||
return -EBADMSG;
|
||||
}
|
||||
|
||||
@@ -1203,7 +1203,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
|
||||
rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY);
|
||||
|
||||
rockchip->hot_rst_wq = create_singlethread_workqueue("rkep_hot_rst_wq");
|
||||
if (rockchip->hot_rst_wq) {
|
||||
if (!rockchip->hot_rst_wq) {
|
||||
dev_err(dev, "failed to create hot_rst workqueue\n");
|
||||
ret = -ENOMEM;
|
||||
goto deinit_phy;
|
||||
|
||||
@@ -30,10 +30,10 @@
|
||||
|
||||
#define DRIVER_NAME "rknpu"
|
||||
#define DRIVER_DESC "RKNPU driver"
|
||||
#define DRIVER_DATE "20230625"
|
||||
#define DRIVER_DATE "20230629"
|
||||
#define DRIVER_MAJOR 0
|
||||
#define DRIVER_MINOR 8
|
||||
#define DRIVER_PATCHLEVEL 9
|
||||
#define DRIVER_MINOR 9
|
||||
#define DRIVER_PATCHLEVEL 0
|
||||
|
||||
#define LOG_TAG "RKNPU"
|
||||
|
||||
|
||||
@@ -73,8 +73,8 @@ enum e_rknpu_mem_type {
|
||||
RKNPU_MEM_ZEROING = 1 << 5,
|
||||
/* allocate secure buffer */
|
||||
RKNPU_MEM_SECURE = 1 << 6,
|
||||
/* allocate from non-dma32 zone */
|
||||
RKNPU_MEM_NON_DMA32 = 1 << 7,
|
||||
/* allocate from dma32 zone */
|
||||
RKNPU_MEM_DMA32 = 1 << 7,
|
||||
/* request SRAM */
|
||||
RKNPU_MEM_TRY_ALLOC_SRAM = 1 << 8,
|
||||
/* request NBUF */
|
||||
@@ -82,7 +82,7 @@ enum e_rknpu_mem_type {
|
||||
RKNPU_MEM_MASK = RKNPU_MEM_NON_CONTIGUOUS | RKNPU_MEM_CACHEABLE |
|
||||
RKNPU_MEM_WRITE_COMBINE | RKNPU_MEM_KERNEL_MAPPING |
|
||||
RKNPU_MEM_IOMMU | RKNPU_MEM_ZEROING |
|
||||
RKNPU_MEM_SECURE | RKNPU_MEM_NON_DMA32 |
|
||||
RKNPU_MEM_SECURE | RKNPU_MEM_DMA32 |
|
||||
RKNPU_MEM_TRY_ALLOC_SRAM | RKNPU_MEM_TRY_ALLOC_NBUF
|
||||
};
|
||||
|
||||
|
||||
@@ -224,7 +224,6 @@ int rknpu_power_get(struct rknpu_device *rknpu_dev)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
cancel_delayed_work(&rknpu_dev->power_off_work);
|
||||
mutex_lock(&rknpu_dev->power_lock);
|
||||
if (atomic_inc_return(&rknpu_dev->power_refcount) == 1)
|
||||
ret = rknpu_power_on(rknpu_dev);
|
||||
@@ -247,6 +246,9 @@ int rknpu_power_put(struct rknpu_device *rknpu_dev)
|
||||
|
||||
static int rknpu_power_put_delay(struct rknpu_device *rknpu_dev)
|
||||
{
|
||||
if (rknpu_dev->power_put_delay == 0)
|
||||
return rknpu_power_put(rknpu_dev);
|
||||
|
||||
mutex_lock(&rknpu_dev->power_lock);
|
||||
if (atomic_read(&rknpu_dev->power_refcount) == 1)
|
||||
queue_delayed_work(
|
||||
@@ -255,6 +257,7 @@ static int rknpu_power_put_delay(struct rknpu_device *rknpu_dev)
|
||||
else
|
||||
atomic_dec_if_positive(&rknpu_dev->power_refcount);
|
||||
mutex_unlock(&rknpu_dev->power_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -67,6 +67,7 @@ static int rknpu_gem_get_pages(struct rknpu_gem_object *rknpu_obj)
|
||||
rknpu_obj->size);
|
||||
goto free_sgt;
|
||||
}
|
||||
iommu_flush_iotlb_all(iommu_get_domain_for_dev(drm->dev));
|
||||
|
||||
if (rknpu_obj->flags & RKNPU_MEM_KERNEL_MAPPING) {
|
||||
rknpu_obj->cookie = vmap(rknpu_obj->pages, rknpu_obj->num_pages,
|
||||
@@ -181,7 +182,9 @@ static int rknpu_gem_alloc_buf(struct rknpu_gem_object *rknpu_obj)
|
||||
if (rknpu_obj->flags & RKNPU_MEM_ZEROING)
|
||||
gfp_mask |= __GFP_ZERO;
|
||||
|
||||
if (!(rknpu_obj->flags & RKNPU_MEM_NON_DMA32)) {
|
||||
if (!rknpu_dev->iommu_en ||
|
||||
rknpu_dev->config->dma_mask <= DMA_BIT_MASK(32) ||
|
||||
(rknpu_obj->flags & RKNPU_MEM_DMA32)) {
|
||||
gfp_mask &= ~__GFP_HIGHMEM;
|
||||
gfp_mask |= __GFP_DMA32;
|
||||
}
|
||||
@@ -360,6 +363,7 @@ static const struct drm_gem_object_funcs rknpu_gem_object_funcs = {
|
||||
static struct rknpu_gem_object *rknpu_gem_init(struct drm_device *drm,
|
||||
unsigned long size)
|
||||
{
|
||||
struct rknpu_device *rknpu_dev = drm->dev_private;
|
||||
struct rknpu_gem_object *rknpu_obj = NULL;
|
||||
struct drm_gem_object *obj = NULL;
|
||||
gfp_t gfp_mask;
|
||||
@@ -388,7 +392,9 @@ static struct rknpu_gem_object *rknpu_gem_init(struct drm_device *drm,
|
||||
if (rknpu_obj->flags & RKNPU_MEM_ZEROING)
|
||||
gfp_mask |= __GFP_ZERO;
|
||||
|
||||
if (!(rknpu_obj->flags & RKNPU_MEM_NON_DMA32)) {
|
||||
if (!rknpu_dev->iommu_en ||
|
||||
rknpu_dev->config->dma_mask <= DMA_BIT_MASK(32) ||
|
||||
(rknpu_obj->flags & RKNPU_MEM_DMA32)) {
|
||||
gfp_mask &= ~__GFP_HIGHMEM;
|
||||
gfp_mask |= __GFP_DMA32;
|
||||
}
|
||||
|
||||
@@ -1198,6 +1198,12 @@ config SPI_SLAVE_SYSTEM_CONTROL
|
||||
SPI slave handler to allow remote control of system reboot, power
|
||||
off, halt, and suspend.
|
||||
|
||||
config SPI_SLAVE_ROCKCHIP_OBJ
|
||||
tristate "Rockchip SPI slave inter transmission protocol demo"
|
||||
help
|
||||
SPI slave with a rockchip protocol specification for SPI slave
|
||||
transmission, work with the corresponding master driver spidev_rkmst.
|
||||
|
||||
endif # SPI_SLAVE
|
||||
|
||||
config SPI_DYNAMIC
|
||||
|
||||
@@ -149,3 +149,5 @@ obj-$(CONFIG_SPI_AMD) += spi-amd.o
|
||||
# SPI slave protocol handlers
|
||||
obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o
|
||||
obj-$(CONFIG_SPI_SLAVE_SYSTEM_CONTROL) += spi-slave-system-control.o
|
||||
obj-$(CONFIG_SPI_SLAVE_ROCKCHIP_OBJ) += spidev-rkslv.o
|
||||
obj-$(CONFIG_SPI_SLAVE_ROCKCHIP_OBJ) += spidev-rkmst.o
|
||||
|
||||
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Reference in New Issue
Block a user