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phy: rockchip: naneng-combphy: Fix swing from 250mV to 650mV for rk3562 pcie

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Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")

Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Jon Lin
2023-07-06 09:36:17 +08:00
committed by Tao Huang
parent b147d4da8f
commit b3a247a0ba
1 changed files with 1 additions and 1 deletions
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2
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -628,7 +628,7 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
writel(0xf0, priv->mmio + (0xa << 2));
/* CKDRV output swing adjust to 650mv */
rockchip_combphy_updatel(priv, GENMASK(4, 1), 0xb, 0xd << 2);
rockchip_combphy_updatel(priv, GENMASK(4, 1), 0xb << 1, 0xd << 2);
}
break;
default: