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ODROID-M1: dtb/dtbo: Add basic alt functions

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Signed-off-by: Steve Jeong <how2soft@gmail.com>
Signed-off-by: Deokgyu Yang <secugyu@gmail.com>
Change-Id: Ic2c21cbbfcf04db21829076db802ad5b656c3aed
This commit is contained in:
Deokgyu Yang
2021-06-24 18:14:14 +09:00
committed by Dongjin Kim
parent f71256902e
commit 19b6649bf7
11 changed files with 173 additions and 0 deletions
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10
arch/arm64/boot/dts/rockchip/overlays/odroidm1/Makefile
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@@ -1,5 +1,15 @@
# Overlays for the Odroid platform
dtbo-$(CONFIG_ARCH_ROCKCHIP_ODROIDM1) += \
i2c0.dtbo \
i2c1.dtbo \
pwm1.dtbo \
pwm2.dtbo \
pwm9.dtbo \
spi0.dtbo \
uart0-with-ctsrts.dtbo \
uart0.dtbo \
uart1.dtbo
targets += $(dtbo-y)
always := $(dtbo-y)

14
arch/arm64/boot/dts/rockchip/overlays/odroidm1/i2c0.dts Normal file
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@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// i2c3 aliased with i2c0.
// This activates i2c3 but it will be named as i2c0 on the userspace.
target = <&i2c3>;
__overlay__ {
status = "okay";
};
};
};

12
arch/arm64/boot/dts/rockchip/overlays/odroidm1/i2c1.dts Normal file
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@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&i2c1>;
__overlay__ {
status = "okay";
};
};
};

13
arch/arm64/boot/dts/rockchip/overlays/odroidm1/pwm1.dts Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// pwmchip0, pwm@fdd70010
target = <&pwm1>;
__overlay__ {
status = "okay";
};
};
};

13
arch/arm64/boot/dts/rockchip/overlays/odroidm1/pwm2.dts Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// pwmchip1, pwm@fdd70020
target = <&pwm2>;
__overlay__ {
status = "okay";
};
};
};

13
arch/arm64/boot/dts/rockchip/overlays/odroidm1/pwm9.dts Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// pwmchip3, pwm@fe6f0010
target = <&pwm9>;
__overlay__ {
status = "okay";
};
};
};

22
arch/arm64/boot/dts/rockchip/overlays/odroidm1/spi0.dts Normal file
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@@ -0,0 +1,22 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&spi0>;
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spidev: spidev@0 {
status = "okay";
compatible = "rockchip,spidev";
reg = <0>;
/* spi default max clock 100Mhz */
spi-max-frequency = <100000000>;
};
};
};
};

14
arch/arm64/boot/dts/rockchip/overlays/odroidm1/uart0-with-ctsrts.dts Normal file
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@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// uart1 aliased with serial0.
target = <&uart1>;
__overlay__ {
status = "okay";
pinctrl-names = "not_use_it", "default";
};
};
};

13
arch/arm64/boot/dts/rockchip/overlays/odroidm1/uart0.dts Normal file
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@@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// uart1 aliased with serial0.
target = <&uart1>;
__overlay__ {
status = "okay";
};
};
};

15
arch/arm64/boot/dts/rockchip/overlays/odroidm1/uart1.dts Normal file
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@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
// uart0 aliased with serial1.
target = <&uart0>;
__overlay__ {
status = "okay";
dma-names = "tx", "rx";
};
};
};

34
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
View File

@@ -152,6 +152,12 @@
"", "", "", "", "", "", "", "";
};
&i2c3 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c3m1_xfer>;
};
&pcie30phy {
status = "okay";
};
@@ -162,6 +168,16 @@
status = "okay";
};
&pwm1 {
status = "disabled";
pinctrl-0 = <&pwm1m1_pins>;
};
&pwm2 {
status = "disabled";
pinctrl-0 = <&pwm2m1_pins>;
};
&sata2 {
status = "okay";
};
@@ -172,3 +188,21 @@
pinctrl-names = "default";
pinctrl-0 = <&fspi_pins>;
};
&spi0 {
status = "disabled";
pinctrl-0 = <&spi0m1_pins>;
pinctrl-1 = <&spi0m1_pins_hs>;
num_chipselect = <1>;
cs-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
};
&uart1 {
status = "disabled";
dma-names = "tx", "rx";
/* uart1 uart1-with-ctsrts */
pinctrl-0 = <&uart1m1_xfer>;
pinctrl-1 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
};