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https://github.com/hardkernel/linux.git
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clock: merge from mainline
PD#SWPL-15312 Change-Id: Icf34b5ebe85efb0565536144df854bc56ebd4791 Signed-off-by: Lei Qian <lei.qian@amlogic.com>
This commit is contained in:
Lei Qian
@@ -25,6 +25,9 @@ Required Properties:
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"amlogic,sm1-clkc-1" - for sm1 ee part1 clock
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"amlogic,sm1-clkc-2" - for sm1 ee part2 clock
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"amlogic,sm1-aoclkc" - for sm1 ao clock
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"amlogic,tm2-clkc" - for tm2 additional ee clock
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"amlogic,tm2-clkc" - for tm2 additional ee clock
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"amlogic,tm2-measure" - for tm2 clock measurement
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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@@ -19,5 +19,6 @@ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a/
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obj-$(CONFIG_AMLOGIC_GX_CLK) += g12b/
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obj-$(CONFIG_AMLOGIC_GX_CLK) += tl1/
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obj-$(CONFIG_AMLOGIC_GX_CLK) += sm1/
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obj-$(CONFIG_AMLOGIC_GX_CLK) += tm2/
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obj-$(CONFIG_AMLOGIC_M8B_CLK) += m8b/
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@@ -176,7 +176,7 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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const struct pll_rate_table *rate_set;
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unsigned long old_rate;
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unsigned int tmp;
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int ret = 0;
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int ret = 0, j = 10;
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u32 reg;
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unsigned long flags = 0;
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@@ -206,54 +206,62 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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}
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}
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if (!strcmp(clk_hw_get_name(hw), "gp0_pll")
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|| !strcmp(clk_hw_get_name(hw), "hifi_pll")
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|| !strcmp(clk_hw_get_name(hw), "pcie_pll")) {
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do {
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void *cntlbase = pll->base + p->reg_off;
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if (!strcmp(clk_hw_get_name(hw), "gp0_pll") ||
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!strcmp(clk_hw_get_name(hw), "hifi_pll") ||
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!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
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if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
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writel(AXG_PCIE_PLL_CNTL,
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cntlbase + (unsigned long)(0 * 4));
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writel(AXG_PCIE_PLL_CNTL1,
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cntlbase + (unsigned long)(1 * 4));
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writel(AXG_PCIE_PLL_CNTL2,
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cntlbase + (unsigned long)(2 * 4));
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writel(AXG_PCIE_PLL_CNTL3,
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cntlbase + (unsigned long)(3 * 4));
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writel(AXG_PCIE_PLL_CNTL4,
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cntlbase + (unsigned long)(4 * 4));
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writel(AXG_PCIE_PLL_CNTL5,
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cntlbase + (unsigned long)(5 * 4));
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writel(AXG_PCIE_PLL_CNTL6,
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cntlbase + (unsigned long)(6 * 4));
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} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
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writel(AXG_HIFI_PLL_CNTL1,
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cntlbase + (unsigned long)(6 * 4));
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writel(AXG_HIFI_PLL_CNTL2,
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cntlbase + (unsigned long)(1 * 4));
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writel(AXG_HIFI_PLL_CNTL3,
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cntlbase + (unsigned long)(2 * 4));
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writel(AXG_HIFI_PLL_CNTL4,
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cntlbase + (unsigned long)(3 * 4));
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writel(AXG_HIFI_PLL_CNTL5,
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cntlbase + (unsigned long)(4 * 4));
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} else {
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writel(GXL_GP0_CNTL1,
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cntlbase + (unsigned long)(6 * 4));
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writel(GXL_GP0_CNTL2,
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cntlbase + (unsigned long)(1 * 4));
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writel(GXL_GP0_CNTL3,
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cntlbase + (unsigned long)(2 * 4));
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writel(GXL_GP0_CNTL4,
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cntlbase + (unsigned long)(3 * 4));
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writel(GXL_GP0_CNTL5,
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cntlbase + (unsigned long)(4 * 4));
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}
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if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
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writel(AXG_PCIE_PLL_CNTL,
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cntlbase + (unsigned long)(0*4));
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writel(AXG_PCIE_PLL_CNTL1,
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cntlbase + (unsigned long)(1*4));
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writel(AXG_PCIE_PLL_CNTL2,
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cntlbase + (unsigned long)(2*4));
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writel(AXG_PCIE_PLL_CNTL3,
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cntlbase + (unsigned long)(3*4));
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writel(AXG_PCIE_PLL_CNTL4,
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cntlbase + (unsigned long)(4*4));
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writel(AXG_PCIE_PLL_CNTL5,
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cntlbase + (unsigned long)(5*4));
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writel(AXG_PCIE_PLL_CNTL6,
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cntlbase + (unsigned long)(6*4));
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} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
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writel(AXG_HIFI_PLL_CNTL1,
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cntlbase + (unsigned long)(6*4));
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writel(AXG_HIFI_PLL_CNTL2,
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cntlbase + (unsigned long)(1*4));
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writel(AXG_HIFI_PLL_CNTL3,
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cntlbase + (unsigned long)(2*4));
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writel(AXG_HIFI_PLL_CNTL4,
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cntlbase + (unsigned long)(3*4));
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writel(AXG_HIFI_PLL_CNTL5,
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cntlbase + (unsigned long)(4*4));
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} else {
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writel(GXL_GP0_CNTL1,
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cntlbase + (unsigned long)(6*4));
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writel(GXL_GP0_CNTL2,
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cntlbase + (unsigned long)(1*4));
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writel(GXL_GP0_CNTL3,
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cntlbase + (unsigned long)(2*4));
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writel(GXL_GP0_CNTL4,
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cntlbase + (unsigned long)(3*4));
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writel(GXL_GP0_CNTL5,
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cntlbase + (unsigned long)(4*4));
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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(~MESON_PLL_RESET)), pll->base + p->reg_off);
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}
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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(~MESON_PLL_RESET)), pll->base + p->reg_off);
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}
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/* waiting for 50us to check is locked or not */
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udelay(50);
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/* lock bit is in the cntlbase */
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if (readl(cntlbase + (unsigned long)(0 * 4))
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& MESON_PLL_LOCK)
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break;
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j--;
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} while (j);
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reg = readl(pll->base + p->reg_off);
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@@ -164,7 +164,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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const struct pll_rate_table *rate_set;
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unsigned long old_rate;
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unsigned int tmp;
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int ret = 0;
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int ret = 0, j = 10;
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u32 reg;
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if (parent_rate == 0 || rate == 0)
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@@ -178,50 +178,57 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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p = &pll->n;
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if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
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do {
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void *cntlbase = pll->base + p->reg_off;
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if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
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if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) ||
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(get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) {
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writel(GXBB_GP0_CNTL2,
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cntlbase + (unsigned long)(1 * 4));
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writel(GXBB_GP0_CNTL3,
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cntlbase + (unsigned long)(2 * 4));
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writel(GXBB_GP0_CNTL4,
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cntlbase + (unsigned long)(3 * 4));
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} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
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writel(GXL_GP0_CNTL1,
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cntlbase + (unsigned long)(6 * 4));
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writel(GXL_GP0_CNTL2,
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cntlbase + (unsigned long)(1 * 4));
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writel(GXL_GP0_CNTL3,
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cntlbase + (unsigned long)(2 * 4));
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writel(GXL_GP0_CNTL4,
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cntlbase + (unsigned long)(3 * 4));
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writel(GXL_GP0_CNTL5,
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cntlbase + (unsigned long)(4 * 4));
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if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) ||
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(get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) {
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writel(GXBB_GP0_CNTL2,
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cntlbase + (unsigned long)(1*4));
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writel(GXBB_GP0_CNTL3,
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cntlbase + (unsigned long)(2*4));
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writel(GXBB_GP0_CNTL4,
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cntlbase + (unsigned long)(3*4));
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} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
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writel(GXL_GP0_CNTL1,
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cntlbase + (unsigned long)(6*4));
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writel(GXL_GP0_CNTL2,
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cntlbase + (unsigned long)(1*4));
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writel(GXL_GP0_CNTL3,
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cntlbase + (unsigned long)(2*4));
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writel(GXL_GP0_CNTL4,
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cntlbase + (unsigned long)(3*4));
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writel(GXL_GP0_CNTL5,
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cntlbase + (unsigned long)(4*4));
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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(~MESON_PLL_RESET)), pll->base + p->reg_off);
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} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
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writel(GXL_GP0_CNTL1,
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cntlbase + (unsigned long)(6*4));
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writel(GXL_GP0_CNTL2,
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cntlbase + (unsigned long)(1*4));
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writel(GXL_GP0_CNTL3,
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cntlbase + (unsigned long)(2*4));
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writel(GXL_GP0_CNTL4,
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cntlbase + (unsigned long)(3*4));
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writel(TXLL_GP0_CNTL5,
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cntlbase + (unsigned long)(4*4));
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} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
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writel(GXL_GP0_CNTL1,
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cntlbase + (unsigned long)(6 * 4));
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writel(GXL_GP0_CNTL2,
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cntlbase + (unsigned long)(1 * 4));
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writel(GXL_GP0_CNTL3,
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cntlbase + (unsigned long)(2 * 4));
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writel(GXL_GP0_CNTL4,
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cntlbase + (unsigned long)(3 * 4));
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writel(TXLL_GP0_CNTL5,
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cntlbase + (unsigned long)(4 * 4));
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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(~MESON_PLL_RESET)), pll->base + p->reg_off);
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}
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}
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}
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/* waiting for 50us to check is locked or not */
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udelay(50);
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/* lock bit is in the cntlbase */
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if (readl(cntlbase + (unsigned long)(0 * 4))
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& MESON_PLL_LOCK)
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break;
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j--;
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} while (j);
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reg = readl(pll->base + p->reg_off);
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@@ -1623,18 +1623,198 @@ static const char * const sm1_table[] = {
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[0] = "am_ring_osc_clk_out_ee[0]",
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};
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static const char * const tm2_table[] = {
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[171] = "pcie1_clk_inn",
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[170] = "pcie1_clk_inp",
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[169] = "pcie0_phy_bs_clk",
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[168] = "pcie1_phy_bs_clk",
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[167] = "au_dac1l_en_dac_clk",
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[166] = "au_dac1r_en_dac_clk",
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[165] = "au_dac2l_en_dac_clk",
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[164] = "au_dac2r_en_dac_clk",
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[163] = "hdmirx_aud_sck",
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[162] = "audio_t0_hdmitx_bclk",
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[161] = "audio_t0_hdmitx_spdif_clk",
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[160] = "dspb_clk",
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[159] = "dspa_clk",
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[157] = "vpu_dmc_clk",
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[156] = "p22_usb2_clkout",
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[155] = "p21_usb2_clkout",
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[154] = "p20_usb2_clkout",
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[153] = "c_alocker_out_clk",
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[152] = "c_alocker_in_clk",
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[151] = "dpll_intclk",
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[150] = "dpll_clk_a2",
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[149] = "dpll_clk_b2",
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[148] = "dpll_clk_b3",
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[147] = "pcie0_clk_inp",
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[146] = "pcie0_clk_inn",
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[145] = "hdmitx_sys_clk",
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[144] = "ts_pll_clk",
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[143] = "mainclk",
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[142] = "demode_ts_clk",
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[141] = "ts_ddr_clk",
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[140] = "audio_toacodec_bclk",
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[139] = "aud_adc_clk_g128x",
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[138] = "vipnanoq_core_clk",
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[137] = "atv_dmd_i2c_sclk",
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[136] = "vipnanoq_axi_clk",
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[135] = "tvfe_sample_clk",
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[134] = "adc_extclk_in",
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[133] = "atv_dmd_mono_clk_32",
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[132] = "audio_toacode_mclk",
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[131] = "ts_sar_clk",
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[130] = "au_dac2_clk_gf128x",
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[129] = "lvds_fifo_clk",
|
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[128] = "cts_tcon_pll_clk",
|
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[127] = "hdmirx_vid_clk",
|
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[126] = "sar_ring_osc_clk",
|
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[125] = "cts_hdmi_axi_clk",
|
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[124] = "cts_demod_core_clk",
|
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[123] = "mod_audio_pdm_dclk_o",
|
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[122] = "audio_spdifin_mst_clk",
|
||||
[121] = "audio_spdifout_mst_clk",
|
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[120] = "audio_spdifout_b_mst_clk",
|
||||
[119] = "audio_pdm_sysclk",
|
||||
[118] = "audio_resamplea_clk",
|
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[117] = "audio_resampleb_clk",
|
||||
[116] = "audio_tdmin_a_sclk",
|
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[115] = "audio_tdmin_b_sclk",
|
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[114] = "audio_tdmin_c_sclk",
|
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[113] = "audio_tdmin_lb_sclk",
|
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[112] = "audio_tdmout_a_sclk",
|
||||
[111] = "audio_tdmout_b_sclk",
|
||||
[110] = "audio_tdmout_c_sclk",
|
||||
[109] = "o_vad_clk",
|
||||
[108] = "acodec_i2sout_bclk",
|
||||
[107] = "au_dac_clk_g128x",
|
||||
[106] = "ephy_test_clk",
|
||||
[105] = "am_ring_osc_clk_out_ee[9]",
|
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[104] = "am_ring_osc_clk_out_ee[8]",
|
||||
[103] = "am_ring_osc_clk_out_ee[7]",
|
||||
[102] = "am_ring_osc_clk_out_ee[6]",
|
||||
[101] = "am_ring_osc_clk_out_ee[5]",
|
||||
[100] = "am_ring_osc_clk_out_ee[4]",
|
||||
[99] = "am_ring_osc_clk_out_ee[3]",
|
||||
[98] = "cts_ts_clk",
|
||||
[97] = "cts_vpu_clkb_tmp",
|
||||
[96] = "cts_vpu_clkb",
|
||||
[95] = "eth_phy_plltxclk",
|
||||
[94] = "eth_phy_exclk",
|
||||
[93] = "sys_cpu_ring_osc_clk[3]",
|
||||
[92] = "sys_cpu_ring_osc_clk[2]",
|
||||
[91] = "hdmirx_audmeas_clk",
|
||||
[90] = "am_ring_osc_clk_out_ee[11]",
|
||||
[89] = "am_ring_osc_clk_out_ee[10]",
|
||||
[88] = "cts_hdmirx_meter_clk",
|
||||
[87] = "hdmitx_tmds_clk",
|
||||
[86] = "cts_hdmirx_modet_clk",
|
||||
[85] = "cts_hdmirx_acr_ref_clk",
|
||||
[84] = "co_tx_cl",
|
||||
[83] = "co_rx_clk",
|
||||
[82] = "cts_ge2d_clk",
|
||||
[81] = "cts_vapbclk",
|
||||
[80] = "rng_ring_osc_clk[3]",
|
||||
[79] = "rng_ring_osc_clk[2]",
|
||||
[78] = "rng_ring_osc_clk[1]",
|
||||
[77] = "rng_ring_osc_clk[0]",
|
||||
[76] = "hdmix_aud_clk",
|
||||
[75] = "cts_hevcf_clk",
|
||||
[74] = "hdmirx_aud_pll_clk",
|
||||
[73] = "cts_pwm_C_clk",
|
||||
[72] = "cts_pwm_D_clk",
|
||||
[71] = "cts_pwm_E_clk",
|
||||
[70] = "cts_pwm_F_clk",
|
||||
[69] = "cts_hdcp22_skpclk",
|
||||
[68] = "cts_hdcp22_esmclk",
|
||||
[67] = "hdmirx_apll_clk_audio",
|
||||
[66] = "cts_vid_lock_clk",
|
||||
[65] = "cts_spicc_0_clk",
|
||||
[64] = "cts_spicc_1_clk",
|
||||
[63] = "hdmirx_tmds_clk",
|
||||
[62] = "cts_hevcb_clk",
|
||||
[61] = "gpio_clk_msr",
|
||||
[60] = "cts_hdmirx_aud_pll_clk",
|
||||
[59] = "cts_hcodec_clk",
|
||||
[58] = "cts_vafe_datack",
|
||||
[57] = "cts_atv_dmd_vdac_clk",
|
||||
[56] = "cts_atv_dmd_sys_clk",
|
||||
[55] = "vid_pll_div_clk_out",
|
||||
[54] = "cts_vpu_clkc",
|
||||
[53] = "ddr_2xclk",
|
||||
[52] = "cts_sd_emmc_clk_B",
|
||||
[51] = "cts_sd_emmc_clk_C",
|
||||
[50] = "mp3_clk_out",
|
||||
[49] = "mp2_clk_out",
|
||||
[48] = "mp1_clk_out",
|
||||
[47] = "ddr_dpll_pt_clk",
|
||||
[46] = "cts_vpu_clk",
|
||||
[45] = "cts_pwm_A_clk",
|
||||
[44] = "cts_pwm_B_clk",
|
||||
[43] = "fclk_div5",
|
||||
[42] = "mp0_clk_out",
|
||||
[41] = "mac_eth_rx_clk_rmii",
|
||||
[40] = "cts_hdmirx_cfg_clk",
|
||||
[39] = "cts_bt656_clk0",
|
||||
[38] = "cts_vdin_meas_clk",
|
||||
[37] = "cts_cdac_clk_c",
|
||||
[36] = "cts_hdmi_tx_pixel_clk",
|
||||
[35] = "cts_mali_clk",
|
||||
[34] = "eth_mppll_50m_ckout",
|
||||
[33] = "sys_cpu_ring_osc_clk[1]",
|
||||
[32] = "cts_vdec_clk",
|
||||
[31] = "mpll_clk_test_out",
|
||||
[30] = "hdmirx_cable_clk",
|
||||
[29] = "hdmirx_apll_clk_out_div",
|
||||
[28] = "cts_sar_adc_clk",
|
||||
[27] = "co_clkin_to_mac",
|
||||
[26] = "sc_clk_int",
|
||||
[25] = "cts_eth_clk_rmii",
|
||||
[24] = "cts_eth_clk125Mhz",
|
||||
[23] = "mpll_clk_50m",
|
||||
[22] = "mac_eth_phy_ref_clk",
|
||||
[21] = "lcd_an_clk_ph3",
|
||||
[20] = "rtc_osc_clk_out",
|
||||
[19] = "lcd_an_clk_ph2",
|
||||
[18] = "sys_cpu_clk_div16",
|
||||
[17] = "sys_pll_div16",
|
||||
[16] = "cts_FEC_CLK_2",
|
||||
[15] = "cts_FEC_CLK_1",
|
||||
[14] = "cts_FEC_CLK_0",
|
||||
[13] = "mod_tcon_clko",
|
||||
[12] = "hifi_pll_clk",
|
||||
[11] = "mac_eth_tx_clk",
|
||||
[10] = "cts_vdac_clk",
|
||||
[9] = "cts_encl_clk",
|
||||
[8] = "cts_encp_clk",
|
||||
[7] = "clk81",
|
||||
[6] = "cts_enci_clk",
|
||||
[5] = "gp1_pll_clk",
|
||||
[4] = "gp0_pll_clk",
|
||||
[3] = "sys_cpu_ring_osc_clk[0]",
|
||||
[2] = "am_ring_osc_clk_out_ee[2]",
|
||||
[1] = "am_ring_osc_clk_out_ee[1]",
|
||||
[0] = "am_ring_osc_clk_out_ee[0]",
|
||||
};
|
||||
|
||||
static const struct meson_clkmsr_data sm1_data = {
|
||||
.clk_table = sm1_table,
|
||||
.table_size = ARRAY_SIZE(sm1_table),
|
||||
.clk_msr_function = gxbb_clk_util_clk_msr,
|
||||
};
|
||||
|
||||
static const struct meson_clkmsr_data tm2_data = {
|
||||
.clk_table = tm2_table,
|
||||
.table_size = ARRAY_SIZE(tm2_table),
|
||||
.clk_msr_function = gxbb_clk_util_clk_msr,
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_clkmsr_dt_match[] = {
|
||||
{ .compatible = "amlogic, gxl_measure",},
|
||||
{ .compatible = "amlogic, m8b_measure",},
|
||||
{ .compatible = "amlogic,tl1-measure", .data = &tl1_data },
|
||||
{ .compatible = "amlogic, sm1-measure", .data = &sm1_data },
|
||||
|
||||
{ .compatible = "amlogic,tm2-measure", .data = &tm2_data },
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
@@ -53,7 +53,7 @@ struct pll_rate_table {
|
||||
u16 n;
|
||||
u16 od;
|
||||
u16 od2;
|
||||
u16 frac;
|
||||
u32 frac;
|
||||
};
|
||||
|
||||
struct fclk_rate_table {
|
||||
|
||||
@@ -1138,19 +1138,6 @@ static void __init g12a_clkc_init(struct device_node *np)
|
||||
goto iounmap;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(np, "own-dsu-clk")) {
|
||||
if (clks[CLKID_DSU_CLK]) {
|
||||
clk_set_parent(clks[CLKID_DSU_CLK],
|
||||
clks[CLKID_CPU_CLK]);
|
||||
/* set sm1_dsu_pre_clk to 1.5G, gp1 pll is 1.5G */
|
||||
clk_set_rate(clks[CLKID_DSU_PRE_CLK], 1500000000);
|
||||
clk_prepare_enable(clks[CLKID_DSU_PRE_CLK]);
|
||||
/* set sm1_dsu_pre_clk as dsu_pre's parent */
|
||||
clk_set_parent(clks[CLKID_DSU_CLK],
|
||||
clks[CLKID_DSU_PRE_CLK]);
|
||||
}
|
||||
}
|
||||
|
||||
pr_debug("%s: cpu clk register notifier ok!", __func__);
|
||||
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
|
||||
@@ -117,6 +117,11 @@
|
||||
#define HHI_SYS1_PLL_CNTL5 0x394 /* 0xe5 offset in data sheet */
|
||||
#define HHI_SYS1_PLL_CNTL6 0x398 /* 0xe6 offset in data sheet */
|
||||
/*****************/
|
||||
|
||||
/* For SM1 only */
|
||||
#define HHI_CSI2_ADAPT_CLK_CNTL 0x3c0 /* 0xf0 offset in data sheet */
|
||||
/*****************/
|
||||
|
||||
#define HHI_BT656_CLK_CNTL 0x3d4 /* 0xf5 offset in data sheet */
|
||||
#define HHI_SPICC_CLK_CNTL 0x3dc /* 0xf7 offset in data sheet */
|
||||
/* AO registers*/
|
||||
|
||||
@@ -51,10 +51,10 @@
|
||||
/* G12A */
|
||||
|
||||
//#define G12A_PCIE_PLL_CNTL 0x400106c8
|
||||
#define G12A_PCIE_PLL_CNTL0_0 0x20090496
|
||||
#define G12A_PCIE_PLL_CNTL0_1 0x30090496
|
||||
#define G12A_PCIE_PLL_CNTL0_2 0x34090496
|
||||
#define G12A_PCIE_PLL_CNTL0_3 0x14090496
|
||||
#define G12A_PCIE_PLL_CNTL0_0 0x28060464
|
||||
#define G12A_PCIE_PLL_CNTL0_1 0x38060464
|
||||
#define G12A_PCIE_PLL_CNTL0_2 0x3c060464
|
||||
#define G12A_PCIE_PLL_CNTL0_3 0x1c060464
|
||||
#define G12A_PCIE_PLL_CNTL1 0x00000000
|
||||
#define G12A_PCIE_PLL_CNTL2 0x00001100
|
||||
#define G12A_PCIE_PLL_CNTL2_ 0x00001000
|
||||
@@ -64,19 +64,6 @@
|
||||
#define G12A_PCIE_PLL_CNTL5 0x68000048
|
||||
#define G12A_PCIE_PLL_CNTL5_ 0x68000068
|
||||
|
||||
#define G12B_PCIE_PLL_CNTL0_0 0x200c04c8
|
||||
#define G12B_PCIE_PLL_CNTL0_1 0x300c04c8
|
||||
#define G12B_PCIE_PLL_CNTL0_2 0x340c04c8
|
||||
#define G12B_PCIE_PLL_CNTL0_3 0x140c04c8
|
||||
#define G12B_PCIE_PLL_CNTL1 0x00000000
|
||||
#define G12B_PCIE_PLL_CNTL2 0x00001100
|
||||
#define G12B_PCIE_PLL_CNTL2_ 0x00001000
|
||||
#define G12B_PCIE_PLL_CNTL3 0x10058e00
|
||||
#define G12B_PCIE_PLL_CNTL4 0x000100c0
|
||||
#define G12B_PCIE_PLL_CNTL4_ 0x008100c0
|
||||
#define G12B_PCIE_PLL_CNTL5 0x68000048
|
||||
#define G12B_PCIE_PLL_CNTL5_ 0x68000068
|
||||
|
||||
#define G12A_SYS_PLL_CNTL1 0x00000000
|
||||
#define G12A_SYS_PLL_CNTL2 0x00000000
|
||||
#define G12A_SYS_PLL_CNTL3 0x48681c00
|
||||
@@ -235,7 +222,7 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
const struct pll_rate_table *rate_set;
|
||||
unsigned long old_rate;
|
||||
unsigned long tmp;
|
||||
int ret = 0;
|
||||
int ret = 0, j = 10;
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
void *cntlbase;
|
||||
@@ -270,106 +257,115 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
cntlbase = pll->base + p->reg_off;
|
||||
|
||||
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
|
||||
writel(G12A_PCIE_PLL_CNTL0_0,
|
||||
cntlbase + (unsigned long)(0*4));
|
||||
writel(G12A_PCIE_PLL_CNTL0_1,
|
||||
cntlbase + (unsigned long)(0*4));
|
||||
writel(G12A_PCIE_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(G12A_PCIE_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(G12A_PCIE_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(G12A_PCIE_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(G12A_PCIE_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(G12A_PCIE_PLL_CNTL5_,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
udelay(20);
|
||||
writel(G12A_PCIE_PLL_CNTL4_,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
udelay(10);
|
||||
/*set pcie_apll_afc_start bit*/
|
||||
writel(G12A_PCIE_PLL_CNTL0_2,
|
||||
cntlbase + (unsigned long)(0*4));
|
||||
writel(G12A_PCIE_PLL_CNTL0_3,
|
||||
cntlbase + (unsigned long)(0*4));
|
||||
udelay(10);
|
||||
writel(G12A_PCIE_PLL_CNTL2_,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
goto OUT;
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_SYS_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(G12A_SYS_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(G12A_SYS_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(G12A_SYS_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(G12A_SYS_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "sys1_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_SYS1_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(G12A_SYS1_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(G12A_SYS1_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(G12A_SYS1_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(G12A_SYS1_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "gp1_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_GP0_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(G12A_GP0_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(G12A_GP0_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(G12A_GP0_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(G12A_GP0_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_HIFI_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(G12A_HIFI_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(G12A_HIFI_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(G12A_HIFI_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(G12A_HIFI_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else {
|
||||
pr_err("%s: %s pll not found!!!\n",
|
||||
__func__, clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
do {
|
||||
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
|
||||
writel(G12A_PCIE_PLL_CNTL0_0,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL0_1,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL5_,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
udelay(20);
|
||||
writel(G12A_PCIE_PLL_CNTL4_,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
udelay(10);
|
||||
/*set pcie_apll_afc_start bit*/
|
||||
writel(G12A_PCIE_PLL_CNTL0_2,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(G12A_PCIE_PLL_CNTL0_3,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
udelay(10);
|
||||
writel(G12A_PCIE_PLL_CNTL2_,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
goto OUT;
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_SYS_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(G12A_SYS_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(G12A_SYS_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(G12A_SYS_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(G12A_SYS_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "sys1_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_SYS1_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(G12A_SYS1_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(G12A_SYS1_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(G12A_SYS1_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(G12A_SYS1_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll") ||
|
||||
!strcmp(clk_hw_get_name(hw), "gp1_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_GP0_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(G12A_GP0_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(G12A_GP0_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(G12A_GP0_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(G12A_GP0_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(G12A_HIFI_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(G12A_HIFI_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(G12A_HIFI_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(G12A_HIFI_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(G12A_HIFI_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(G12A_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else {
|
||||
pr_err("%s: %s pll not found!!!\n",
|
||||
__func__, clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
/* waiting for 50us to check is locked or not */
|
||||
udelay(50);
|
||||
/* lock bit is in the cntlbase */
|
||||
if (readl(cntlbase + (unsigned long)(0 * 4))
|
||||
& MESON_PLL_LOCK)
|
||||
break;
|
||||
j--;
|
||||
} while (j);
|
||||
|
||||
reg = readl(pll->base + p->reg_off);
|
||||
|
||||
|
||||
@@ -26,6 +26,7 @@
|
||||
#include "../clkc.h"
|
||||
#include "../g12a/g12a.h"
|
||||
#include "sm1.h"
|
||||
#include <linux/delay.h>
|
||||
|
||||
static struct meson_clk_pll sm1_gp1_pll = {
|
||||
.m = {
|
||||
@@ -140,6 +141,99 @@ static struct clk_gate cts_vipnanoq_axi_clk_gate = {
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const media_parent_names_mipi[] = { "xtal",
|
||||
"gp0_pll", "mpll1", "mpll2", "fclk_div3", "fclk_div4",
|
||||
"fclk_div5", "fclk_div7"
|
||||
};
|
||||
|
||||
static struct clk_mux cts_mipi_csi_phy_clk_mux = {
|
||||
.reg = (void *)HHI_MIPI_CSI_PHY_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_mipi_csi_phy_clk_mux",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = media_parent_names_mipi,
|
||||
.num_parents = 8,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider cts_mipi_csi_phy_clk_div = {
|
||||
.reg = (void *)HHI_MIPI_CSI_PHY_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_mipi_csi_phy_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "cts_mipi_csi_phy_clk_mux" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate cts_mipi_csi_phy_clk_gate = {
|
||||
.reg = (void *)HHI_MIPI_CSI_PHY_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mipi_csi_phy_clk_gate",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_mipi_csi_phy_clk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const media_parent_names_adapt[] = { "xtal",
|
||||
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2",
|
||||
"mpll3", "gp0_pll"
|
||||
};
|
||||
|
||||
static struct clk_mux cts_csi_adapt_clk_mux = {
|
||||
.reg = (void *)HHI_CSI2_ADAPT_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_csi_adapt_clk_mux",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = media_parent_names_adapt,
|
||||
.num_parents = 8,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider cts_csi_adapt_clk_div = {
|
||||
.reg = (void *)HHI_CSI2_ADAPT_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_csi_adapt_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "cts_csi_adapt_clk_mux" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate cts_csi_adapt_clk_gate = {
|
||||
.reg = (void *)HHI_CSI2_ADAPT_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_csi_adapt_clk_gate",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_csi_adapt_clk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_mux sm1_dsu_pre_src_clk_mux0 = {
|
||||
.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
|
||||
.mask = 0x3,
|
||||
@@ -151,7 +245,7 @@ static struct clk_mux sm1_dsu_pre_src_clk_mux0 = {
|
||||
.parent_names = (const char *[]){ "xtal", "fclk_div2",
|
||||
"fclk_div3", "gp1_pll" },
|
||||
.num_parents = 4,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -166,7 +260,7 @@ static struct clk_mux sm1_dsu_pre_src_clk_mux1 = {
|
||||
.parent_names = (const char *[]){ "xtal", "fclk_div2",
|
||||
"fclk_div3", "gp1_pll" },
|
||||
.num_parents = 4,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -330,12 +424,53 @@ static struct clk_hw *sm1_clk_hws[] = {
|
||||
&sm1_csi_phy.hw,
|
||||
};
|
||||
|
||||
struct sm1_nb_data {
|
||||
struct notifier_block nb;
|
||||
};
|
||||
|
||||
static int sm1_dsu_mux_clk_notifier_cb(struct notifier_block *nb,
|
||||
unsigned long event, void *data)
|
||||
{
|
||||
struct clk *dsu_pre_clk, *parent_clk;
|
||||
int ret;
|
||||
|
||||
switch (event) {
|
||||
case PRE_RATE_CHANGE:
|
||||
/* switch to sm1_dsu_fixed_sel1, set it to 1G (default 24M) */
|
||||
ret = clk_set_rate(sm1_dsu_pre_clk_mux1.hw.clk, 1000000000);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
parent_clk = sm1_dsu_pre_clk_mux1.hw.clk;
|
||||
break;
|
||||
case POST_RATE_CHANGE:
|
||||
parent_clk = sm1_dsu_pre_clk_mux0.hw.clk;
|
||||
break;
|
||||
default:
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
dsu_pre_clk = sm1_dsu_pre_post_clk_mux.hw.clk;
|
||||
|
||||
ret = clk_set_parent(dsu_pre_clk, parent_clk);
|
||||
if (ret)
|
||||
return notifier_from_errno(ret);
|
||||
|
||||
usleep_range(80, 120);
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct sm1_nb_data sm1_dsu_nb_data = {
|
||||
.nb.notifier_call = sm1_dsu_mux_clk_notifier_cb,
|
||||
};
|
||||
|
||||
static void __init sm1_clkc_init(struct device_node *np)
|
||||
{
|
||||
int ret = 0, clkid, i;
|
||||
|
||||
if (!clk_base)
|
||||
clk_base = of_iomap(np, 0);
|
||||
|
||||
if (!clk_base) {
|
||||
pr_err("%s: Unable to map clk base\n", __func__);
|
||||
return;
|
||||
@@ -373,6 +508,20 @@ static void __init sm1_clkc_init(struct device_node *np)
|
||||
+ (unsigned long)(cts_vipnanoq_axi_clk_gate.reg);
|
||||
cts_vipnanoq_axi_clk_div.reg = clk_base
|
||||
+ (unsigned long)(cts_vipnanoq_axi_clk_div.reg);
|
||||
|
||||
cts_mipi_csi_phy_clk_mux.reg = clk_base
|
||||
+ (unsigned long)(cts_mipi_csi_phy_clk_mux.reg);
|
||||
cts_mipi_csi_phy_clk_div.reg = clk_base
|
||||
+ (unsigned long)(cts_mipi_csi_phy_clk_div.reg);
|
||||
cts_mipi_csi_phy_clk_gate.reg = clk_base
|
||||
+ (unsigned long)(cts_mipi_csi_phy_clk_gate.reg);
|
||||
cts_csi_adapt_clk_mux.reg = clk_base
|
||||
+ (unsigned long)(cts_csi_adapt_clk_mux.reg);
|
||||
cts_csi_adapt_clk_div.reg = clk_base
|
||||
+ (unsigned long)(cts_csi_adapt_clk_div.reg);
|
||||
cts_csi_adapt_clk_gate.reg = clk_base
|
||||
+ (unsigned long)(cts_csi_adapt_clk_gate.reg);
|
||||
|
||||
/* Populate base address for gates */
|
||||
for (i = 0; i < ARRAY_SIZE(sm1_clk_gates); i++)
|
||||
sm1_clk_gates[i]->reg = clk_base +
|
||||
@@ -426,17 +575,47 @@ static void __init sm1_clkc_init(struct device_node *np)
|
||||
if (IS_ERR(clks[CLKID_VNANOQ_AXI_CLK_COMP]))
|
||||
panic("%s: %d register cts_vipnanoq_axi_clk_composite error\n",
|
||||
__func__, __LINE__);
|
||||
if (clks[CLKID_CPU_CLK]) {
|
||||
if (!of_property_read_bool(np, "own-dsu-clk"))
|
||||
return;
|
||||
/* set cpu clk as dsu_clk's parent*/
|
||||
clk_set_parent(sm1_dsu_clk.hw.clk, clks[CLKID_CPU_CLK]);
|
||||
/* set sm1_dsu_pre_clk to 1.5G, gp1 pll is 1.5G */
|
||||
clk_set_rate(sm1_dsu_pre_clk.hw.clk, 1500000000);
|
||||
clk_prepare_enable(sm1_dsu_pre_clk.hw.clk);
|
||||
/* set sm1_dsu_pre_clk as dsu_clk's parent */
|
||||
clk_set_parent(sm1_dsu_clk.hw.clk, sm1_dsu_pre_clk.hw.clk);
|
||||
|
||||
clks[CLKID_MIPI_CSI_PHY_CLK_COMP] = clk_register_composite(NULL,
|
||||
"cts_csi_phy_clk_composite",
|
||||
media_parent_names_mipi, 8,
|
||||
&cts_mipi_csi_phy_clk_mux.hw,
|
||||
&clk_mux_ops,
|
||||
&cts_mipi_csi_phy_clk_div.hw,
|
||||
&clk_divider_ops,
|
||||
&cts_mipi_csi_phy_clk_gate.hw,
|
||||
&clk_gate_ops, 0);
|
||||
if (IS_ERR(clks[CLKID_MIPI_CSI_PHY_CLK_COMP]))
|
||||
panic("%s: %d register cts_csi_phy_clk_composite error\n",
|
||||
__func__, __LINE__);
|
||||
|
||||
clks[CLKID_CSI_ADAPT_CLK_COMP] = clk_register_composite(NULL,
|
||||
"cts_csi_adapt_clk_composite",
|
||||
media_parent_names_adapt, 8,
|
||||
&cts_csi_adapt_clk_mux.hw,
|
||||
&clk_mux_ops,
|
||||
&cts_csi_adapt_clk_div.hw,
|
||||
&clk_divider_ops,
|
||||
&cts_csi_adapt_clk_gate.hw,
|
||||
&clk_gate_ops, 0);
|
||||
if (IS_ERR(clks[CLKID_CSI_ADAPT_CLK_COMP]))
|
||||
panic("%s: %d register cts_csi_adapt_clk_composite error\n",
|
||||
__func__, __LINE__);
|
||||
|
||||
if (of_property_read_bool(np, "own-dsu-clk")) {
|
||||
/*
|
||||
* when change sm1_dsu_pre_clk_mux0, switch to
|
||||
* sm1_dsu_pre_clk_mux1 to avoid crash
|
||||
*/
|
||||
ret = clk_notifier_register(sm1_dsu_pre_clk_mux0.hw.clk,
|
||||
&sm1_dsu_nb_data.nb);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to register clock notifier for cpu_clk\n",
|
||||
__func__);
|
||||
goto iounmap;
|
||||
}
|
||||
}
|
||||
pr_err("sm1 clk probe ok\n");
|
||||
return;
|
||||
|
||||
iounmap:
|
||||
@@ -445,5 +624,3 @@ iounmap:
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(sm1, "amlogic,sm1-clkc-2", sm1_clkc_init);
|
||||
|
||||
|
||||
|
||||
@@ -14,7 +14,6 @@
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
@@ -22,6 +21,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/amlogic,tl1-clkc.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "../clkc.h"
|
||||
#include "tl1.h"
|
||||
@@ -107,13 +107,13 @@ static struct meson_clk_pll tl1_gp1_pll = {
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_GP1_PLL_CNTL0,
|
||||
.shift = 9,
|
||||
.shift = 10,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = HHI_GP1_PLL_CNTL0,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
.width = 3,
|
||||
},
|
||||
.rate_table = tl1_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(tl1_pll_rate_table),
|
||||
@@ -185,6 +185,10 @@ static struct meson_clk_pll tl1_adc_pll = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct pll_rate_table tl1_fixed_pll_rate_table[] = {
|
||||
PLL_FRAC_RATE(2000000000ULL, 166, 1, 1, 0, 0x3F15555),
|
||||
};
|
||||
|
||||
static struct meson_clk_pll tl1_fixed_pll = {
|
||||
.m = {
|
||||
.reg_off = HHI_FIX_PLL_CNTL0,
|
||||
@@ -207,12 +211,14 @@ static struct meson_clk_pll tl1_fixed_pll = {
|
||||
.width = 19,
|
||||
},
|
||||
.lock = &clk_lock,
|
||||
.rate_table = tl1_fixed_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(tl1_fixed_pll_rate_table),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fixed_pll",
|
||||
.ops = &meson_tl1_pll_ro_ops,
|
||||
.ops = &meson_tl1_pll_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -447,8 +453,8 @@ static struct meson_cpu_mux_divider tl1_cpu_fclk_p = {
|
||||
.name = "cpu_fixedpll_p",
|
||||
.ops = &meson_fclk_cpu_ops,
|
||||
.parent_names = (const char *[]){ "xtal", "fclk_div2",
|
||||
"fclk_div3"},
|
||||
.num_parents = 3,
|
||||
"fclk_div3", "gp1_pll"},
|
||||
.num_parents = 4,
|
||||
.flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
|
||||
},
|
||||
};
|
||||
@@ -676,6 +682,19 @@ static struct clk_gate tl1_clk81 = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_mux tl1_switch_clk81 = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "switch_clk81",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = (const char *[]){ "xtal", "clk81" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
/* HHI_GCLK_MPEG0 26 bits valid */
|
||||
static MESON_GATE_TL1(tl1_ddr, HHI_GCLK_MPEG0, 0);
|
||||
@@ -841,7 +860,7 @@ static struct clk_hw *tl1_clk_hws[] = {
|
||||
[CLKID_BT656] = &tl1_bt656.hw, /*MPEG2 6*/
|
||||
[CLKID_USB1_TO_DDR] = &tl1_usb1_to_ddr.hw, /*MPEG2 8*/
|
||||
[CLKID_MMC_PCLK] = &tl1_mmc_pclk.hw, /*MPEG2 11*/
|
||||
[CLKID_HDCP22_PCLK] = &tl1_hdcp22_pclk.hw, /*MPEG2 13*/
|
||||
[CLKID_HDMIRX_TOP] = &tl1_hdcp22_pclk.hw, /*MPEG2 13*/
|
||||
[CLKID_UART2] = &tl1_uart2.hw, /*MPEG2 15*/
|
||||
[CLKID_TS] = &tl1_ts.hw, /*MPEG2 22*/
|
||||
[CLKID_VPU_INTR] = &tl1_vpu_intr.hw, /*MPEG2 25*/
|
||||
@@ -1080,6 +1099,31 @@ static void __init tl1_clkc_init(struct device_node *np)
|
||||
tl1_cpu_clk.reg = clk_base
|
||||
+ (unsigned long)tl1_cpu_clk.reg;
|
||||
|
||||
/* Populate the base address for DSU clk */
|
||||
tl1_dsu_fixed_source_sel0.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_fixed_source_sel0.reg;
|
||||
tl1_dsu_fixed_source_div0.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_fixed_source_div0.reg;
|
||||
tl1_dsu_fixed_sel0.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_fixed_sel0.reg;
|
||||
|
||||
tl1_dsu_fixed_source_sel1.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_fixed_source_sel1.reg;
|
||||
tl1_dsu_fixed_source_div1.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_fixed_source_div1.reg;
|
||||
tl1_dsu_fixed_sel1.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_fixed_sel1.reg;
|
||||
|
||||
tl1_dsu_pre0_clk.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_pre0_clk.reg;
|
||||
tl1_dsu_pre_clk.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_pre_clk.reg;
|
||||
tl1_dsu_clk.reg = clk_base
|
||||
+ (unsigned long)tl1_dsu_clk.reg;
|
||||
|
||||
tl1_switch_clk81.reg = clk_base
|
||||
+ (unsigned long)tl1_switch_clk81.reg;
|
||||
|
||||
/* Populate base address for gates */
|
||||
for (i = 0; i < ARRAY_SIZE(tl1_clk_gates); i++)
|
||||
tl1_clk_gates[i]->reg = clk_base +
|
||||
@@ -1102,10 +1146,12 @@ static void __init tl1_clkc_init(struct device_node *np)
|
||||
/*register all clks*/
|
||||
for (clkid = 0; clkid < CLOCK_GATE; clkid++) {
|
||||
if (tl1_clk_hws[clkid]) {
|
||||
clks[clkid] = clk_register(NULL, tl1_clk_hws[clkid]);
|
||||
WARN_ON(IS_ERR(clks[clkid]));
|
||||
clks[clkid] = clk_register(NULL, tl1_clk_hws[clkid]);
|
||||
WARN_ON(IS_ERR(clks[clkid]));
|
||||
}
|
||||
}
|
||||
clks[CLKID_SWITCH_CLK81] = clk_register(NULL, &tl1_switch_clk81.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_SWITCH_CLK81]));
|
||||
|
||||
meson_tl1_sdemmc_init();
|
||||
meson_tl1_media_init();
|
||||
@@ -1142,6 +1188,11 @@ static void __init tl1_clkc_init(struct device_node *np)
|
||||
goto iounmap;
|
||||
}
|
||||
|
||||
/* fixed pll init */
|
||||
ret = clk_prepare_enable(tl1_fixed_pll.hw.clk);
|
||||
if (ret)
|
||||
pr_err("%s, failed to init fixed pll\n", __func__);
|
||||
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
&clk_data);
|
||||
if (ret < 0) {
|
||||
|
||||
@@ -50,13 +50,13 @@
|
||||
#define HHI_HIFI_PLL_CNTL6 0xec /* 0x3b offset in datasheet */
|
||||
#define HHI_HIFI_PLL_STS 0xf0 /* 0x3c offset in datasheet very*/
|
||||
|
||||
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in datasheet */
|
||||
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in datasheet */
|
||||
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in datasheet */
|
||||
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in datasheet */
|
||||
#define HHI_GCLK_MPEG0 0xc0 /* 0x30 offset in datasheet */
|
||||
#define HHI_GCLK_MPEG1 0xc4 /* 0x31 offset in datasheet */
|
||||
#define HHI_GCLK_MPEG2 0xc8 /* 0x32 offset in datasheet */
|
||||
#define HHI_GCLK_OTHER 0xd0 /* 0x34 offset in datasheet */
|
||||
|
||||
#define HHI_GCLK_AO 0x154 /* 0x55 offset in datasheet */
|
||||
|
||||
#define HHI_SYS_CPU_CLK_CNTL1 0x15C /* 0x57 offset in datasheet1 */
|
||||
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in datasheet */
|
||||
#define HHI_SPICC_HCLK_CNTL 0x168 /* 0x5a offset in datasheet */
|
||||
|
||||
@@ -70,7 +70,7 @@
|
||||
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in datasheet */
|
||||
#define HHI_VPU_CLKC_CNTL 0x1b4 /* 0x6d offset in datasheet1 */
|
||||
#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in datasheet1 */
|
||||
#define HHI_AUDPLL_CLK_OUT_CNTL 0x1E0 /* 0x74 offset in datasheet1 */
|
||||
#define HHI_AUDPLL_CLK_OUT_CNTL 0x1E0 /* 0x74 offset in datasheet1 */
|
||||
#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in datasheet1 */
|
||||
#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in datasheet1 */
|
||||
#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in datasheet1 */
|
||||
@@ -80,6 +80,9 @@
|
||||
#define HHI_HDMIRX_CLK_CNTL 0x200 /* 0x80 offset in datasheet1 */
|
||||
#define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x81 offset in datasheet1 */
|
||||
#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in datasheet1 */
|
||||
#define HHI_SYS_CPU_CLK_CNTL5 0x21C /* 0x87 offset in datasheet1 */
|
||||
#define HHI_SYS_CPU_CLK_CNTL6 0x220 /* 0x88 offset in datasheet1 */
|
||||
#define HHI_HDMIRX_METER_CLK_CNTL 0x234 /* 0x8d offset in datasheet1 */
|
||||
|
||||
#define HHI_VDIN_MEAS_CLK_CNTL 0x250 /* 0x94 offset in datasheet1 */
|
||||
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in datasheet1*/
|
||||
|
||||
@@ -172,7 +172,7 @@ static int tl1_aoclkc_probe(struct platform_device *pdev)
|
||||
tl1_saradc_div.reg = aoclk_base + (unsigned long)tl1_saradc_div.reg;
|
||||
tl1_saradc_gate.reg = aoclk_base + (unsigned long)tl1_saradc_gate.reg;
|
||||
|
||||
for (clkid = CLKID_AO_BASE; clkid < NR_CLKS; clkid++) {
|
||||
for (clkid = CLKID_AO_BASE; clkid < CLKID_AO_END; clkid++) {
|
||||
if (tl1_ao_clk_hws[clkid-CLKID_AO_BASE]) {
|
||||
clks[clkid] = clk_register(NULL,
|
||||
tl1_ao_clk_hws[clkid-CLKID_AO_BASE]);
|
||||
|
||||
@@ -55,6 +55,14 @@
|
||||
#define TL1_SYS_PLL_CNTL4 0x88770290
|
||||
#define TL1_SYS_PLL_CNTL5 0x39272000
|
||||
|
||||
#define TL1_FIXED_PLL_CNTL0 0xD00104A6
|
||||
#define TL1_FIXED_PLL_CNTL1 0x3F15555
|
||||
#define TL1_FIXED_PLL_CNTL2 0x00000000
|
||||
#define TL1_FIXED_PLL_CNTL3 0x6A285C60
|
||||
#define TL1_FIXED_PLL_CNTL4 0x65771290
|
||||
#define TL1_FIXED_PLL_CNTL5 0x39272000
|
||||
#define TL1_FIXED_PLL_CNTL6 0x56540000
|
||||
#define TL1_FIXED_PLL_TST 0xA000004F
|
||||
|
||||
#define TL1_GP0_PLL_CNTL1 0x00000000
|
||||
#define TL1_GP0_PLL_CNTL2 0x00000000
|
||||
@@ -70,6 +78,20 @@
|
||||
|
||||
#define TL1_PLL_CNTL6 0x56540000
|
||||
|
||||
#define TM2_PCIE_PLL_CNTL0_0 0x280c0464
|
||||
#define TM2_PCIE_PLL_CNTL0_1 0x380c0464
|
||||
#define TM2_PCIE_PLL_CNTL0_2 0x3c0c0464
|
||||
#define TM2_PCIE_PLL_CNTL0_3 0x1c0c0464
|
||||
#define TM2_PCIE_PLL_CNTL0_4 0x140c04c8
|
||||
#define TM2_PCIE_PLL_CNTL1 0x30000000
|
||||
#define TM2_PCIE_PLL_CNTL2 0x00001100
|
||||
#define TM2_PCIE_PLL_CNTL2_ 0x00001000
|
||||
#define TM2_PCIE_PLL_CNTL3 0x10058e00
|
||||
#define TM2_PCIE_PLL_CNTL4 0x000100c0
|
||||
#define TM2_PCIE_PLL_CNTL4_ 0x008100c0
|
||||
#define TM2_PCIE_PLL_CNTL5 0x68000048
|
||||
#define TM2_PCIE_PLL_CNTL5_ 0x68000068
|
||||
|
||||
#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
|
||||
|
||||
static unsigned long meson_tl1_pll_recalc_rate(struct clk_hw *hw,
|
||||
@@ -146,14 +168,26 @@ static long meson_tl1_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
struct meson_clk_pll *pll = to_meson_clk_pll(hw);
|
||||
const struct pll_rate_table *rate_table = pll->rate_table;
|
||||
int i;
|
||||
u64 ret_rate = 0;
|
||||
|
||||
for (i = 0; i < pll->rate_count; i++) {
|
||||
if (rate <= rate_table[i].rate)
|
||||
return rate_table[i].rate;
|
||||
if (rate <= rate_table[i].rate) {
|
||||
ret_rate = rate_table[i].rate;
|
||||
if (!strcmp(clk_hw_get_name(hw), "sys_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "fixed_pll"))
|
||||
do_div(ret_rate, 1000);
|
||||
|
||||
return ret_rate;
|
||||
}
|
||||
}
|
||||
|
||||
/* else return the smallest value */
|
||||
return rate_table[0].rate;
|
||||
ret_rate = rate_table[0].rate;
|
||||
if (!strcmp(clk_hw_get_name(hw), "sys_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "fixed_pll"))
|
||||
do_div(ret_rate, 1000);
|
||||
|
||||
return ret_rate;
|
||||
}
|
||||
|
||||
static const struct pll_rate_table *meson_tl1_get_pll_settings
|
||||
@@ -197,10 +231,15 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
void *cntlbase;
|
||||
int j = 10;
|
||||
|
||||
if (parent_rate == 0 || rate == 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (!strcmp(clk_hw_get_name(hw), "sys_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "fixed_pll"))
|
||||
rate *= 1000;
|
||||
|
||||
old_rate = rate;
|
||||
|
||||
rate_set = meson_tl1_get_pll_settings(pll, rate);
|
||||
@@ -225,60 +264,117 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
cntlbase = pll->base + p->reg_off;
|
||||
|
||||
|
||||
if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(TL1_SYS_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(TL1_SYS_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(TL1_SYS_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(TL1_SYS_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(TL1_SYS_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(TL1_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(TL1_GP0_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(TL1_GP0_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(TL1_GP0_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(TL1_GP0_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(TL1_GP0_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(TL1_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(TL1_GP0_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1*4));
|
||||
writel(TL1_GP0_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2*4));
|
||||
writel(TL1_GP0_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3*4));
|
||||
writel(TL1_GP0_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4*4));
|
||||
writel(TL1_GP0_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5*4));
|
||||
writel(TL1_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6*4));
|
||||
udelay(10);
|
||||
} else {
|
||||
pr_err("%s: %s pll not found!!!\n",
|
||||
__func__, clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
do {
|
||||
if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(TL1_SYS_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(TL1_SYS_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(TL1_SYS_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(TL1_SYS_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(TL1_SYS_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(TL1_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll") ||
|
||||
!strcmp(clk_hw_get_name(hw), "gp1_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(TL1_GP0_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(TL1_GP0_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(TL1_GP0_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(TL1_GP0_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(TL1_GP0_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(TL1_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
writel(TL1_HIFI_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(TL1_HIFI_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(TL1_HIFI_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(TL1_HIFI_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(TL1_HIFI_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(TL1_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
|
||||
writel(TM2_PCIE_PLL_CNTL0_0,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL0_1,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(7 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(8 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(53 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(54 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL5_,
|
||||
cntlbase + (unsigned long)(54 * 4));
|
||||
udelay(20);
|
||||
writel(TM2_PCIE_PLL_CNTL4_,
|
||||
cntlbase + (unsigned long)(53 * 4));
|
||||
udelay(10);
|
||||
/*set pcie_apll_afc_start bit*/
|
||||
writel(TM2_PCIE_PLL_CNTL0_2,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL0_3,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
udelay(20);
|
||||
writel(TM2_PCIE_PLL_CNTL0_4,
|
||||
cntlbase + (unsigned long)(0 * 4));
|
||||
writel(TM2_PCIE_PLL_CNTL2_,
|
||||
cntlbase + (unsigned long)(7 * 4));
|
||||
} else if (!strcmp(clk_hw_get_name(hw), "fixed_pll")) {
|
||||
writel((readl(cntlbase) | MESON_PLL_RESET)
|
||||
& (~MESON_PLL_ENABLE), cntlbase);
|
||||
udelay(100);
|
||||
writel(TL1_FIXED_PLL_CNTL1,
|
||||
cntlbase + (unsigned long)(1 * 4));
|
||||
writel(TL1_FIXED_PLL_CNTL2,
|
||||
cntlbase + (unsigned long)(2 * 4));
|
||||
writel(TL1_FIXED_PLL_CNTL3,
|
||||
cntlbase + (unsigned long)(3 * 4));
|
||||
writel(TL1_FIXED_PLL_CNTL4,
|
||||
cntlbase + (unsigned long)(4 * 4));
|
||||
writel(TL1_FIXED_PLL_CNTL5,
|
||||
cntlbase + (unsigned long)(5 * 4));
|
||||
writel(TL1_FIXED_PLL_CNTL6,
|
||||
cntlbase + (unsigned long)(6 * 4));
|
||||
udelay(10);
|
||||
} else {
|
||||
pr_err("%s: %s pll not found!!!\n",
|
||||
__func__, clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
/* waiting for 50us to check is locked or not */
|
||||
udelay(50);
|
||||
/* lock bit is in the cntlbase */
|
||||
if (readl(cntlbase + (unsigned long)(0 * 4))
|
||||
& MESON_PLL_LOCK)
|
||||
break;
|
||||
j--;
|
||||
} while (j);
|
||||
|
||||
reg = readl(pll->base + p->reg_off);
|
||||
|
||||
@@ -320,7 +416,6 @@ static int meson_tl1_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
reg = PARM_SET(p->width, p->shift, reg, tmp);
|
||||
writel(reg, pll->base + p->reg_off);
|
||||
}
|
||||
|
||||
p = &pll->n;
|
||||
|
||||
/* PLL reset */
|
||||
@@ -366,8 +461,10 @@ static int meson_tl1_pll_enable(struct clk_hw *hw)
|
||||
}
|
||||
|
||||
if (!strcmp(clk_hw_get_name(hw), "gp0_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "gp1_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "hifi_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "sys_pll")) {
|
||||
|| !strcmp(clk_hw_get_name(hw), "sys_pll")
|
||||
|| !strcmp(clk_hw_get_name(hw), "fixed_pll")) {
|
||||
void *cntlbase = pll->base + p->reg_off;
|
||||
|
||||
if (readl(cntlbase + (unsigned long)(6*4))
|
||||
@@ -375,7 +472,6 @@ static int meson_tl1_pll_enable(struct clk_hw *hw)
|
||||
first_set = 0;
|
||||
|
||||
}
|
||||
|
||||
parent = clk_hw_get_parent(hw);
|
||||
|
||||
/*First init, just set minimal rate.*/
|
||||
@@ -403,6 +499,9 @@ static void meson_tl1_pll_disable(struct clk_hw *hw)
|
||||
if (pll->lock)
|
||||
spin_lock_irqsave(pll->lock, flags);
|
||||
|
||||
if (!strcmp(clk_hw_get_name(hw), "fixed_pll"))
|
||||
pr_warn("Pay Attention, fixed pll will be disabled\n");
|
||||
|
||||
writel(readl(pll->base + p->reg_off) | (MESON_PLL_RESET),
|
||||
pll->base + p->reg_off);
|
||||
writel(readl(pll->base + p->reg_off) & (~MESON_PLL_ENABLE),
|
||||
|
||||
5
drivers/amlogic/clk/tm2/Makefile
Normal file
5
drivers/amlogic/clk/tm2/Makefile
Normal file
@@ -0,0 +1,5 @@
|
||||
#
|
||||
# Makefile for Meson TL1 clk
|
||||
#
|
||||
|
||||
obj-$(CONFIG_AMLOGIC_GX_CLK) += tm2.o
|
||||
271
drivers/amlogic/clk/tm2/tm2.c
Normal file
271
drivers/amlogic/clk/tm2/tm2.c
Normal file
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/tm2/tm2.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/amlogic,tl1-clkc.h>
|
||||
|
||||
#include "../clkc.h"
|
||||
#include "../tl1/tl1.h"
|
||||
#include "tm2.h"
|
||||
|
||||
static const struct pll_rate_table tm2_pcie_pll_rate_table[] = {
|
||||
PLL_RATE(100000000, 200, 1, 12),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct meson_clk_pll tm2_pcie_pll = {
|
||||
.m = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 10,
|
||||
.width = 5,
|
||||
},
|
||||
.od = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 16,
|
||||
.width = 5,
|
||||
},
|
||||
.frac = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL1,
|
||||
.shift = 0,
|
||||
.width = 12,
|
||||
},
|
||||
.rate_table = tm2_pcie_pll_rate_table,
|
||||
.rate_count = ARRAY_SIZE(tm2_pcie_pll_rate_table),
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie_pll",
|
||||
.ops = &meson_tl1_pll_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_GET_RATE_NOCACHE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate tm2_pcie01_enable = {
|
||||
.reg = (void *)HHI_PCIE_PLL_CNTL1,
|
||||
.bit_idx = 29,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tm2_pcie01",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "pcie_pll" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate tm2_pcie0_gate = {
|
||||
.reg = (void *)HHI_PCIE_PLL_CNTL5,
|
||||
.bit_idx = 3,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tm2_pcie0_gate",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "tm2_pcie01" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate tm2_pcie1_gate = {
|
||||
.reg = (void *)HHI_PCIE_PLL_CNTL1,
|
||||
.bit_idx = 28,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "tm2_pcie1_gate",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "tm2_pcie01" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
|
||||
},
|
||||
};
|
||||
|
||||
/* clk81 gate for tm2 */
|
||||
static MESON_GATE(tm2_vipnanoq, HHI_GCLK_MPEG1, 19);
|
||||
static MESON_GATE(tm2_pcie1, HHI_GCLK_MPEG1, 24);
|
||||
static MESON_GATE(tm2_pcie1phy, HHI_GCLK_MPEG1, 27);
|
||||
static MESON_GATE(tm2_parserl, HHI_GCLK_MPEG1, 28);
|
||||
static MESON_GATE(tm2_hdcp22_pclk, HHI_GCLK_MPEG2, 3);
|
||||
static MESON_GATE(tm2_hdmitx_pclk, HHI_GCLK_MPEG2, 4);
|
||||
static MESON_GATE(tm2_pcie0, HHI_GCLK_MPEG2, 6);
|
||||
static MESON_GATE(tm2_pcie0phy, HHI_GCLK_MPEG2, 7);
|
||||
static MESON_GATE(tm2_hdmirx_axi_pclk, HHI_GCLK_MPEG2, 12);
|
||||
static MESON_GATE(tm2_dspb, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(tm2_dspa, HHI_GCLK_MPEG2, 27);
|
||||
|
||||
PNAME(dsp_parent_names) = { "fclk_div2", "fclk_div3",
|
||||
"fclk_div5", "fclk_div7", "xtal", "gp0_pll", "gp1_pll", "hifi_pll" };
|
||||
|
||||
static MUX(dspa_clk_a_mux, HHI_DSP_CLK_CNTL, 0x7, 4,
|
||||
dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(dspa_clk_a_div, HHI_DSP_CLK_CNTL, 0, 4, "dspa_clk_a_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
static GATE(dspa_clk_a_gate, HHI_DSP_CLK_CNTL, 7, "dspa_clk_a_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
|
||||
static MUX(dspa_clk_b_mux, HHI_DSP_CLK_CNTL, 0x7, 12,
|
||||
dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(dspa_clk_b_div, HHI_DSP_CLK_CNTL, 8, 4, "dspa_clk_b_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
static GATE(dspa_clk_b_gate, HHI_DSP_CLK_CNTL, 7, "dspa_clk_b_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
|
||||
PNAME(dspa_parent_names) = { "dspa_clk_a_gate",
|
||||
"dspa_clk_b_gate" };
|
||||
|
||||
static MESON_MUX(dspa_clk_mux, HHI_DSP_CLK_CNTL, 0x1, 15,
|
||||
dspa_parent_names, CLK_GET_RATE_NOCACHE);
|
||||
|
||||
|
||||
static MUX(dspb_clk_a_mux, HHI_DSP_CLK_CNTL, 0x7, 20,
|
||||
dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(dspb_clk_a_div, HHI_DSP_CLK_CNTL, 16, 4, "dspb_clk_a_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
static GATE(dspb_clk_a_gate, HHI_DSP_CLK_CNTL, 23, "dspb_clk_a_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
|
||||
static MUX(dspb_clk_b_mux, HHI_DSP_CLK_CNTL, 0x7, 28,
|
||||
dsp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(dspb_clk_b_div, HHI_DSP_CLK_CNTL, 24, 4, "dspb_clk_b_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
static GATE(dspb_clk_b_gate, HHI_DSP_CLK_CNTL, 23, "dspb_clk_b_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT);
|
||||
|
||||
PNAME(dspb_parent_names) = { "dspb_clk_a_gate",
|
||||
"dspb_clk_b_gate" };
|
||||
|
||||
static MESON_MUX(dspb_clk_mux, HHI_DSP_CLK_CNTL, 0x1, 31,
|
||||
dspb_parent_names, CLK_GET_RATE_NOCACHE);
|
||||
|
||||
static struct clk_gate *tm2_clk_gates[] = {
|
||||
&tm2_vipnanoq,
|
||||
&tm2_pcie1,
|
||||
&tm2_pcie1phy,
|
||||
&tm2_parserl,
|
||||
&tm2_hdcp22_pclk,
|
||||
&tm2_hdmitx_pclk,
|
||||
&tm2_pcie0phy,
|
||||
&tm2_hdmirx_axi_pclk,
|
||||
&tm2_dspb,
|
||||
&tm2_dspa,
|
||||
&dspa_clk_a_gate,
|
||||
&dspa_clk_b_gate,
|
||||
&dspb_clk_a_gate,
|
||||
&dspb_clk_b_gate,
|
||||
&tm2_pcie0_gate,
|
||||
&tm2_pcie1_gate,
|
||||
&tm2_pcie0,
|
||||
&tm2_pcie01_enable,
|
||||
};
|
||||
|
||||
static struct clk_mux *tm2_clk_mux[] = {
|
||||
&dspa_clk_a_mux,
|
||||
&dspa_clk_b_mux,
|
||||
&dspb_clk_a_mux,
|
||||
&dspb_clk_b_mux,
|
||||
&dspa_clk_mux,
|
||||
&dspb_clk_mux,
|
||||
};
|
||||
|
||||
static struct clk_divider *tm2_clk_divs[] = {
|
||||
&dspa_clk_a_div,
|
||||
&dspa_clk_b_div,
|
||||
&dspb_clk_a_div,
|
||||
&dspb_clk_b_div,
|
||||
};
|
||||
|
||||
/* Array of all clocks provided by this provider */
|
||||
static struct clk_hw *tm2_clk_hws[] = {
|
||||
[CLKID_PCIE_PLL] = &tm2_pcie_pll.hw,
|
||||
[CLKID_VIPNANOQ] = &tm2_vipnanoq.hw,
|
||||
[CLKID_PCIE0] = &tm2_pcie0.hw,
|
||||
[CLKID_PCIE1] = &tm2_pcie1.hw,
|
||||
[CLKID_PCIE1PHY] = &tm2_pcie1phy.hw,
|
||||
[CLKID_PARSER1] = &tm2_parserl.hw,
|
||||
[CLKID_HDCP22_PCLK] = &tm2_hdcp22_pclk.hw,
|
||||
[CLKID_HDMITX_PCLK] = &tm2_hdmitx_pclk.hw,
|
||||
[CLKID_PCIE0PHY] = &tm2_pcie0phy.hw,
|
||||
[CLKID_HDMITX_AXI_PCLK] = &tm2_hdmirx_axi_pclk.hw,
|
||||
[CLKID_DSPB] = &tm2_dspb.hw,
|
||||
[CLKID_DSPA] = &tm2_dspa.hw,
|
||||
[CLKID_DSPA_MUX_A] = &dspa_clk_a_mux.hw,
|
||||
[CLKID_DSPA_DIV_A] = &dspa_clk_a_div.hw,
|
||||
[CLKID_DSPA_GATE_A] = &dspa_clk_a_gate.hw,
|
||||
[CLKID_DSPA_MUX_B] = &dspa_clk_b_mux.hw,
|
||||
[CLKID_DSPA_DIV_B] = &dspa_clk_b_div.hw,
|
||||
[CLKID_DSPA_GATE_B] = &dspa_clk_b_gate.hw,
|
||||
[CLKID_DSPA_MUX] = &dspa_clk_mux.hw,
|
||||
[CLKID_DSPB_MUX_A] = &dspb_clk_a_mux.hw,
|
||||
[CLKID_DSPB_DIV_A] = &dspb_clk_a_div.hw,
|
||||
[CLKID_DSPB_GATE_A] = &dspb_clk_a_gate.hw,
|
||||
[CLKID_DSPB_MUX_B] = &dspb_clk_b_mux.hw,
|
||||
[CLKID_DSPB_DIV_B] = &dspb_clk_b_div.hw,
|
||||
[CLKID_DSPB_GATE_B] = &dspb_clk_b_gate.hw,
|
||||
[CLKID_DSPB_MUX] = &dspb_clk_mux.hw,
|
||||
[CLKID_PCIE01_ENABLE] = &tm2_pcie01_enable.hw,
|
||||
[CLKID_PCIE0_GATE] = &tm2_pcie0_gate.hw,
|
||||
[CLKID_PCIE1_GATE] = &tm2_pcie1_gate.hw,
|
||||
};
|
||||
|
||||
static void __init tm2_clkc_init(struct device_node *np)
|
||||
{
|
||||
int clkid, i;
|
||||
|
||||
if (!clk_base) {
|
||||
pr_err("tm2 clock basic clock driver not prepare\n");
|
||||
WARN_ON(IS_ERR(clk_base));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Populate base address for pcie pll */
|
||||
tm2_pcie_pll.base = clk_base;
|
||||
|
||||
/* Populate base address for media muxes */
|
||||
for (i = 0; i < ARRAY_SIZE(tm2_clk_mux); i++)
|
||||
tm2_clk_mux[i]->reg = clk_base +
|
||||
(unsigned long)tm2_clk_mux[i]->reg;
|
||||
|
||||
/* Populate base address for media divs */
|
||||
for (i = 0; i < ARRAY_SIZE(tm2_clk_divs); i++)
|
||||
tm2_clk_divs[i]->reg = clk_base +
|
||||
(unsigned long)tm2_clk_divs[i]->reg;
|
||||
|
||||
/* Populate base address for gates */
|
||||
for (i = 0; i < ARRAY_SIZE(tm2_clk_gates); i++)
|
||||
tm2_clk_gates[i]->reg = clk_base +
|
||||
(unsigned long)tm2_clk_gates[i]->reg;
|
||||
|
||||
/* register tm2 clks, pcie pll is the first clock index */
|
||||
for (clkid = CLKID_PCIE_PLL; clkid < GATE_BASE0; clkid++) {
|
||||
if (tm2_clk_hws[clkid]) {
|
||||
clks[clkid] = clk_register(NULL, tm2_clk_hws[clkid]);
|
||||
WARN_ON(IS_ERR(clks[clkid]));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(tm2, "amlogic,tm2-clkc", tm2_clkc_init);
|
||||
37
drivers/amlogic/clk/tm2/tm2.h
Normal file
37
drivers/amlogic/clk/tm2/tm2.h
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/tm2/tm2.h
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __TM2_H
|
||||
#define __TM2_H
|
||||
|
||||
/*
|
||||
* Clock controller register offsets
|
||||
*
|
||||
* Register offsets from the data sheet are listed in comment blocks below.
|
||||
* Those offsets must be multiplied by 4 before adding them to the base address
|
||||
* to get the right value
|
||||
*/
|
||||
#define HHI_PCIE_PLL_CNTL0 0x94 /* 0x25 offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL1 0x98 /* 0x26 offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL2 0xb0 /* 0x2c offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL3 0xb4 /* 0x2d offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL4 0x168 /* 0x5a offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL5 0x16c /* 0x5b offset in data sheet */
|
||||
#define HHI_PCIE_PLL_STS 0x170 /* 0x5c offset in data sheet */
|
||||
#define HHI_DSP_CLK_CNTL 0x3f0 /* 0xfc offset in data sheet */
|
||||
|
||||
#endif /* __TL1_H */
|
||||
@@ -315,8 +315,10 @@
|
||||
#define CLKID_CSI_ADPAT_CLK (CLKID_SM1_ADD_BASE + 14)
|
||||
#define CLKID_TEMP_SENSOR_CLK (CLKID_SM1_ADD_BASE + 15)
|
||||
#define CLKID_CSI_PHY_CLK (CLKID_SM1_ADD_BASE + 16)
|
||||
#define CLKID_MIPI_CSI_PHY_CLK_COMP (CLKID_SM1_ADD_BASE + 17)
|
||||
#define CLKID_CSI_ADAPT_CLK_COMP (CLKID_SM1_ADD_BASE + 18)
|
||||
|
||||
#define CLKID_AO_BASE (CLKID_SM1_ADD_BASE + 17)
|
||||
#define CLKID_AO_BASE (CLKID_SM1_ADD_BASE + 19)
|
||||
#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
|
||||
#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
|
||||
#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)
|
||||
|
||||
@@ -39,18 +39,50 @@
|
||||
#define CLKID_MPLL1 15
|
||||
#define CLKID_MPLL2 16
|
||||
#define CLKID_MPLL3 17
|
||||
#define CLKID_CPU_FCLK_P00 18
|
||||
#define CLKID_CPU_FCLK_P01 19
|
||||
#define CLKID_CPU_FCLK_P0 20
|
||||
#define CLKID_CPU_FCLK_P10 21
|
||||
#define CLKID_CPU_FCLK_P11 22
|
||||
#define CLKID_CPU_FCLK_P1 23
|
||||
#define CLKID_CPU_FCLK_P 24
|
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#define CLKID_CPU_CLK 25
|
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#define CLKID_CPU_FCLK_P 18
|
||||
#define CLKID_CPU_CLK 19
|
||||
#define CLKID_DSU_SOURCE_SEL0 20
|
||||
#define CLKID_DSU_SOURCE_DIV0 21
|
||||
#define CLKID_DSU_SEL0 22
|
||||
#define CLKID_DSU_SOURCE_SEL1 23
|
||||
#define CLKID_DSU_SOURCE_DIV1 24
|
||||
#define CLKID_DSU_SEL1 25
|
||||
#define CLKID_DSU_PRE_PARENT0 26
|
||||
#define CLKID_DSU_PRE_CLK 27
|
||||
#define CLKID_DSU_CLK 28
|
||||
/*#define CLKID_ADC_PLL 24*/
|
||||
|
||||
#define CLKID_PCIE_PLL 29
|
||||
#define CLKID_VIPNANOQ 30
|
||||
#define CLKID_PCIE1 31
|
||||
#define CLKID_PCIE0PHY 32
|
||||
#define CLKID_PCIE1PHY 33
|
||||
#define CLKID_PARSER1 34
|
||||
#define CLKID_HDCP22_PCLK 35
|
||||
#define CLKID_HDMITX_PCLK 36
|
||||
#define CLKID_HDMITX_AXI_PCLK 37
|
||||
#define CLKID_DSPB 38
|
||||
#define CLKID_DSPA 39
|
||||
/* dsp clocks */
|
||||
#define CLKID_DSPA_MUX_A 40
|
||||
#define CLKID_DSPA_DIV_A 41
|
||||
#define CLKID_DSPA_GATE_A 42
|
||||
#define CLKID_DSPA_MUX_B 43
|
||||
#define CLKID_DSPA_DIV_B 44
|
||||
#define CLKID_DSPA_GATE_B 45
|
||||
#define CLKID_DSPA_MUX 46
|
||||
#define CLKID_DSPB_MUX_A 47
|
||||
#define CLKID_DSPB_DIV_A 48
|
||||
#define CLKID_DSPB_GATE_A 49
|
||||
#define CLKID_DSPB_MUX_B 50
|
||||
#define CLKID_DSPB_DIV_B 51
|
||||
#define CLKID_DSPB_GATE_B 52
|
||||
#define CLKID_DSPB_MUX 53
|
||||
#define CLKID_PCIE0_GATE 54
|
||||
#define CLKID_PCIE1_GATE 55
|
||||
#define CLKID_PCIE0 56
|
||||
#define CLKID_PCIE01_ENABLE 57
|
||||
/*HHI_GCLK_MPEG0: 0x50*/
|
||||
#define GATE_BASE0 (26)
|
||||
#define GATE_BASE0 58
|
||||
|
||||
#define CLKID_DDR (GATE_BASE0 + 0)
|
||||
#define CLKID_DOS (GATE_BASE0 + 1)
|
||||
@@ -102,7 +134,7 @@
|
||||
#define CLKID_BT656 (GATE_BASE2 + 2)
|
||||
#define CLKID_USB1_TO_DDR (GATE_BASE2 + 3)
|
||||
#define CLKID_MMC_PCLK (GATE_BASE2 + 4)
|
||||
#define CLKID_HDCP22_PCLK (GATE_BASE0 + 5)
|
||||
#define CLKID_HDMIRX_TOP (GATE_BASE0 + 5)
|
||||
#define CLKID_UART2 (GATE_BASE2 + 6)
|
||||
#define CLKID_TS (GATE_BASE2 + 7)
|
||||
#define CLKID_VPU_INTR (GATE_BASE2 + 8)
|
||||
@@ -129,7 +161,6 @@
|
||||
#define CLKID_VCLK2_VENCLMMC (GATE_OTHER + 14)
|
||||
#define CLKID_VCLK2_VENCL (GATE_OTHER + 15)
|
||||
#define CLKID_VCLK2_OTHER1 (GATE_OTHER + 16)
|
||||
|
||||
/*HHI_GCLK_OTHER: 0x55*/
|
||||
#define GATE_AO_BASE (GATE_OTHER + 17)
|
||||
|
||||
@@ -265,5 +296,8 @@
|
||||
#define CLKID_AO_UART2 (CLKID_AO_BASE + 10)
|
||||
#define CLKID_AO_IR_BLASTER (CLKID_AO_BASE + 11)
|
||||
#define CLKID_AO_SAR_ADC (CLKID_AO_BASE + 12)
|
||||
#define NR_CLKS (CLKID_AO_BASE + 13)
|
||||
#define CLKID_AO_END (CLKID_AO_BASE + 13)
|
||||
#define CLKID_SWITCH_CLK81 (CLKID_AO_BASE + 13)
|
||||
#define NR_CLKS (CLKID_AO_BASE + 14)
|
||||
|
||||
#endif /* __DT_BINDINGS_TL1_CLKC_H */
|
||||
|
||||
Reference in New Issue
Block a user