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arm64: dts: rockchip: rk3576-vehicle-evb-v20-serdes-mfd-display-maxim: remove assigned VPLL clk rate

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VPLL is initialized at uboot for dclk, If kernel assigned VPLL clk rate
and different with uboot set rate, this will lead to VPLL reinitialized
and lead to splash screen.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I501bf982b6016841ea046325d692aee73618357b
This commit is contained in:
Sandy Huang
2025-03-20 15:43:13 +08:00
committed by Tao Huang
parent 635a7a4081
commit 1c2dcc6d2b
1 changed files with 0 additions and 5 deletions
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arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi
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@@ -1690,11 +1690,6 @@
status = "okay";
};
&vop {
assigned-clocks = <&cru PLL_VPLL>;
assigned-clock-rates = <1150000000>;
};
//edp
&vp0 {
assigned-clocks = <&cru DCLK_VP0_SRC>;