shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 11:50:43 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: optimizing ddrclk_scpi_recalc_rate behavior

Browse Source 
Cat ddr frequency from rockchip_ddrclk_scpi_set_rate prior to
rockchip_ddrclk_scpi_recalc_rate, to optimizing running time and reduce
SCPI APIs usage rate.

Change-Id: Iba31d33a5920816b1cc230f639ea3a9503d451c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Tang Yun ping
2017-04-06 15:25:12 +08:00
committed by Tao Huang
parent 9c8373f109
commit 1dfb2c15c6
1 changed files with 13 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/clk/rockchip/clk-ddr.c
View File

@@ -100,6 +100,8 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
.get_parent = rockchip_ddrclk_get_parent,
};
static u32 ddr_clk_cached;
static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
@@ -107,6 +109,13 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
u32 lcdc_type = 7;
ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
if (ret) {
ddr_clk_cached = ret;
ret = 0;
} else {
ddr_clk_cached = 0;
ret = -1;
}
return ret;
}
@@ -114,7 +123,10 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return (MHZ * scpi_ddr_get_clk_rate());
if (ddr_clk_cached)
return (MHZ * ddr_clk_cached);
else
return (MHZ * scpi_ddr_get_clk_rate());
}
static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw,