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soc: rockchip: rockchip_system_monitor: Make mem volt greater than vdd volt
The vdd is the power supply of pvtpll, if mem volt less than vdd volt, there will not be enough voltage margin. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I15b57904c20b74d16ac8113f3e49e3410bcf02af
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@@ -1338,6 +1338,15 @@ int rockchip_monitor_check_rate_volt(struct monitor_dev_info *info)
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rockchip_set_intermediate_rate(dev, opp_info, info->clk,
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old_rate, new_rate,
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true, is_set_clk);
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if (old_volt > new_volt) {
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ret = regulator_set_voltage(vdd_reg, new_volt, INT_MAX);
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if (ret) {
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dev_err(dev, "%s: failed to set volt: %lu\n",
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__func__, new_volt);
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goto restore_voltage;
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}
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}
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if (info->regulator_count > 1) {
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ret = regulator_set_voltage(mem_reg, new_mem_volt,
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INT_MAX);
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@@ -1347,11 +1356,13 @@ int rockchip_monitor_check_rate_volt(struct monitor_dev_info *info)
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goto restore_voltage;
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}
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}
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ret = regulator_set_voltage(vdd_reg, new_volt, INT_MAX);
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if (ret) {
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dev_err(dev, "%s: failed to set volt: %lu\n",
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__func__, new_volt);
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goto restore_voltage;
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if (old_volt <= new_volt) {
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ret = regulator_set_voltage(vdd_reg, new_volt, INT_MAX);
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if (ret) {
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dev_err(dev, "%s: failed to set volt: %lu\n",
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__func__, new_volt);
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goto restore_voltage;
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}
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}
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rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm);
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if (is_set_clk && clk_set_rate(info->clk, new_rate)) {
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@@ -1396,9 +1407,12 @@ restore_rm:
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rockchip_get_read_margin(dev, opp_info, old_volt, &target_rm);
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rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm);
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restore_voltage:
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if (old_volt <= new_volt)
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regulator_set_voltage(vdd_reg, old_volt, INT_MAX);
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if (info->regulator_count > 1)
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regulator_set_voltage(mem_reg, old_mem_volt, INT_MAX);
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regulator_set_voltage(vdd_reg, old_volt, INT_MAX);
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if (old_volt > new_volt)
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regulator_set_voltage(vdd_reg, old_volt, INT_MAX);
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disable_clk:
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rockchip_monitor_disable_opp_clk(dev, opp_info);
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unlock:
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