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clk: rockchip: rk3588: export clk_phy0/1_ref_alt_p/m clk id

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I149c43cd77f777c9d45c095be8c0c77c126b56d2
This commit is contained in:
Elaine Zhang
2021-12-02 11:11:23 +08:00
committed by Tao Huang
parent e2a2addf37
commit 1f57d9eb1b
2 changed files with 15 additions and 1 deletions
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10
drivers/clk/rockchip/clk-rk3588.c
View File

@@ -14,6 +14,7 @@
#include "clk.h"
#define RK3588_GRF_SOC_STATUS0 0x600
#define RK3588_PHYREF_ALT_GATE 0xc38
#define RK3588_FRAC_MAX_PRATE 1500000000
#define RK3588_DCLK_MAX_PRATE 400000000
@@ -2256,6 +2257,15 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 0, GFLAGS),
GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 1, GFLAGS),
GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 2, GFLAGS),
GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
RK3588_PHYREF_ALT_GATE, 3, GFLAGS),
GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 12, GFLAGS),
GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,

6
include/dt-bindings/clock/rk3588-cru.h
View File

@@ -709,8 +709,12 @@
#define CLK_CORE_LITCORE_PVTM 715
#define CLK_AUX16M_0 716
#define CLK_AUX16M_1 717
#define CLK_PHY0_REF_ALT_P 718
#define CLK_PHY0_REF_ALT_M 719
#define CLK_PHY1_REF_ALT_P 720
#define CLK_PHY1_REF_ALT_M 721
#define CLK_NR_CLKS (CLK_AUX16M_1 + 1)
#define CLK_NR_CLKS (CLK_PHY1_REF_ALT_M + 1)
/********Name=SOFTRST_CON01,Offset=0xA04********/
#define SRST_A_TOP_BIU 19