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arm64: dts: rockchip: rk3576-vehicle-evb-v20: max96712 d(/c)phy0(/3): add more sensor dtsi

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dummy: MAX96717, DUMMY, 1920 * 1440, YUV422 8bit
isx021: MAX96717F, ISX021, 1920 * 1281, YUV422 8bit

Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: Ic8b0ff43e376a9697c82092190de46c07bcf8eb8
This commit is contained in:
Cai Wenzhong
2024-12-17 11:26:39 +08:00
parent 058b229588
commit 1f97a95049
5 changed files with 3581 additions and 0 deletions
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709
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dcphy0-dummy.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
/ {
max96712_dcphy0_osc: max96712-dcphy0-oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "max96712-dcphy0-osc";
};
max96712_dcphy0_vcc1v2: max96712-dcphy0-vcc1v2 {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_vcc1v2";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
startup-delay-us = <850>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dcphy0_vcc1v8: max96712-dcphy0-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_vcc1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dcphy0_pwdn_regulator: max96712-dcphy0-pwdn-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_pwdn";
gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dcphy0_pwdn>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
};
max96712_dcphy0_poc_regulator: max96712-dcphy0-poc-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_poc";
gpio = <&i2c7_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
vin-supply = <&dcphy0_vcc12v_buck1>;
};
};
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dcphy0_in_max96712: endpoint@1 {
reg = <1>;
remote-endpoint = <&max96712_dcphy0_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m1_xfer>;
max96712_dcphy0: max96712@29 {
compatible = "maxim4c,max96712";
status = "okay";
reg = <0x29>;
clock-names = "xvclk";
clocks = <&max96712_dcphy0_osc 0>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dcphy0_errb>, <&max96712_dcphy0_lock>;
power-domains = <&power RK3576_PD_VI>;
rockchip,grf = <&sys_grf>;
vcc1v2-supply = <&max96712_dcphy0_vcc1v2>;
vcc1v8-supply = <&max96712_dcphy0_vcc1v8>;
pwdn-supply = <&max96712_dcphy0_pwdn_regulator>;
lock-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
max96712_dcphy0_out: endpoint {
remote-endpoint = <&mipi_dcphy0_in_max96712>;
data-lanes = <1 2 3 4>;
};
};
/* support mode config start */
support-mode-config {
status = "okay";
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
sensor-width = <1920>;
sensor-height = <1440>;
max-fps-numerator = <10000>;
max-fps-denominator = <300000>;
bpp = <16>;
link-freq-idx = <20>;
};
/* support mode config end */
/* serdes local device start */
serdes-local-device {
status = "okay";
/* GMSL LINK config start */
gmsl-links {
status = "okay";
link-vdd-ldo1-en = <1>;
link-vdd-ldo2-en = <1>;
// Link A: link-id = 0
gmsl-link-config-0 {
status = "okay";
link-id = <0>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam0>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
14 D1 03 00 00 // VGAHiGain
14 45 00 00 00 // Disable SSC
];
};
};
// Link B: link-id = 1
gmsl-link-config-1 {
status = "okay";
link-id = <1>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam1>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
15 D1 03 00 00 // VGAHiGain
15 45 00 00 00 // Disable SSC
];
};
};
// Link C: link-id = 2
gmsl-link-config-2 {
status = "okay";
link-id = <2>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam2>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
16 D1 03 00 00 // VGAHiGain
16 45 00 00 00 // Disable SSC
];
};
};
// Link D: link-id = 3
gmsl-link-config-3 {
status = "okay";
link-id = <3>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam3>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
17 D1 03 00 00 // VGAHiGain
17 45 00 00 00 // Disable SSC
];
};
};
};
/* GMSL LINK config end */
/* VIDEO PIPE config start */
video-pipes {
status = "okay";
// Video Pipe 0
video-pipe-config-0 {
status = "okay";
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
];
};
};
// Video Pipe 1
video-pipe-config-1 {
status = "okay";
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
];
};
};
// Video Pipe 2
video-pipe-config-2 {
status = "okay";
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
];
};
};
// Video Pipe 3
video-pipe-config-3 {
status = "okay";
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
];
};
};
};
/* VIDEO PIPE config end */
/* MIPI TXPHY config start */
mipi-txphys {
status = "okay";
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
phy-force-clock-out = <1>; // 1: default for force clock out
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
// MIPI TXPHY A: phy-id = 0
mipi-txphy-config-0 {
status = "okay";
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0x4>;
vc-ext-en = <0>;
};
// MIPI TXPHY B: phy-id = 1
mipi-txphy-config-1 {
status = "okay";
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0xe>;
vc-ext-en = <0>;
};
};
/* MIPI TXPHY config end */
/* local device extra init sequence */
extra-init-sequence {
status = "disabled";
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// common init sequence such as fsync / gpio and so on
];
};
};
/* serdes local device end */
/* i2c-mux start */
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser0: max96717@51 {
compatible = "maxim,ser,max96717";
reg = <0x51>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam0: dummy@31 {
compatible = "maxim,dummy,sensor";
reg = <0x31>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser0>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam0_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser1: max96717@52 {
compatible = "maxim,ser,max96717";
reg = <0x52>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam1: dummy@32 {
compatible = "maxim,dummy,sensor";
reg = <0x32>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser1>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam1_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser2: max96717@53 {
compatible = "maxim,ser,max96717";
reg = <0x53>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam2: dummy@33 {
compatible = "maxim,dummy,sensor";
reg = <0x33>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser2>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam2_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser3: max96717@54 {
compatible = "maxim,ser,max96717";
reg = <0x54>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam3: dummy@34 {
compatible = "maxim,dummy,sensor";
reg = <0x34>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser3>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam3_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
};
/* i2c-mux end */
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi0_in>;
};
};
};
};
&rkcif_mipi_lvds {
status = "okay";
/* parameters for do cif reset detecting:
* index0: monitor mode,
0 for idle,
1 for continue,
2 for trigger,
3 for hotplug (for nextchip)
* index1: the frame id to start timer,
min is 2
* index2: frame num of monitoring cycle
* index3: err time for keep monitoring
after finding out err (ms)
* index4: csi2 err reference val for resetting
*/
rockchip,cif-monitor = <3 2 1 1000 5>;
port {
cif_mipi0_in: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif {
status = "okay";
rockchip,android-usb-camerahal-enable;
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
max96712-dcphy0 {
max96712_dcphy0_pwdn: max96712-dcphy0-pwdn {
rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dcphy0_errb: max96712-dcphy0-errb {
rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dcphy0_lock: max96712-dcphy0-lock {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

721
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dcphy0-isx021.dtsi Normal file
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@@ -0,0 +1,721 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
/ {
max96712_dcphy0_osc: max96712-dcphy0-oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "max96712-dcphy0-osc";
};
max96712_dcphy0_vcc1v2: max96712-dcphy0-vcc1v2 {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_vcc1v2";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
startup-delay-us = <850>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dcphy0_vcc1v8: max96712-dcphy0-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_vcc1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dcphy0_pwdn_regulator: max96712-dcphy0-pwdn-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_pwdn";
gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dcphy0_pwdn>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
};
max96712_dcphy0_poc_regulator: max96712-dcphy0-poc-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_poc";
gpio = <&i2c7_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
vin-supply = <&dcphy0_vcc12v_buck1>;
};
};
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dcphy0_in_max96712: endpoint@1 {
reg = <1>;
remote-endpoint = <&max96712_dcphy0_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m1_xfer>;
max96712_dcphy0: max96712@29 {
compatible = "maxim4c,max96712";
status = "okay";
reg = <0x29>;
clock-names = "xvclk";
clocks = <&max96712_dcphy0_osc 0>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dcphy0_errb>, <&max96712_dcphy0_lock>;
power-domains = <&power RK3576_PD_VI>;
rockchip,grf = <&sys_grf>;
vcc1v2-supply = <&max96712_dcphy0_vcc1v2>;
vcc1v8-supply = <&max96712_dcphy0_vcc1v8>;
pwdn-supply = <&max96712_dcphy0_pwdn_regulator>;
lock-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
max96712_dcphy0_out: endpoint {
remote-endpoint = <&mipi_dcphy0_in_max96712>;
data-lanes = <1 2 3 4>;
};
};
/* support mode config start */
support-mode-config {
status = "okay";
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
sensor-width = <1920>;
sensor-height = <1281>;
crop-rect = <0 1 1920 1280>; // [ left, top, width, height ]
max-fps-numerator = <10000>;
max-fps-denominator = <300000>;
bpp = <16>;
link-freq-idx = <20>;
};
/* support mode config end */
/* serdes local device start */
serdes-local-device {
status = "okay";
/* GMSL LINK config start */
gmsl-links {
status = "okay";
link-vdd-ldo1-en = <1>;
link-vdd-ldo2-en = <1>;
// Link A: link-id = 0
gmsl-link-config-0 {
status = "okay";
link-id = <0>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam0>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
14 D1 03 00 00 // VGAHiGain
14 45 00 00 00 // Disable SSC
];
};
};
// Link B: link-id = 1
gmsl-link-config-1 {
status = "okay";
link-id = <1>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam1>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
15 D1 03 00 00 // VGAHiGain
15 45 00 00 00 // Disable SSC
];
};
};
// Link C: link-id = 2
gmsl-link-config-2 {
status = "okay";
link-id = <2>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam2>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
16 D1 03 00 00 // VGAHiGain
16 45 00 00 00 // Disable SSC
];
};
};
// Link D: link-id = 3
gmsl-link-config-3 {
status = "okay";
link-id = <3>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam3>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
17 D1 03 00 00 // VGAHiGain
17 45 00 00 00 // Disable SSC
];
};
};
};
/* GMSL LINK config end */
/* VIDEO PIPE config start */
video-pipes {
status = "okay";
// Video Pipe 0
video-pipe-config-0 {
status = "okay";
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
];
};
};
// Video Pipe 1
video-pipe-config-1 {
status = "okay";
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
];
};
};
// Video Pipe 2
video-pipe-config-2 {
status = "okay";
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
];
};
};
// Video Pipe 3
video-pipe-config-3 {
status = "okay";
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
];
};
};
};
/* VIDEO PIPE config end */
/* MIPI TXPHY config start */
mipi-txphys {
status = "okay";
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
phy-force-clock-out = <1>; // 1: default for force clock out
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
// MIPI TXPHY A: phy-id = 0
mipi-txphy-config-0 {
status = "okay";
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0x4>;
vc-ext-en = <0>;
};
// MIPI TXPHY B: phy-id = 1
mipi-txphy-config-1 {
status = "okay";
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0xe>;
vc-ext-en = <0>;
};
};
/* MIPI TXPHY config end */
/* local device extra init sequence */
extra-init-sequence {
status = "okay";
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// common init sequence such as fsync / gpio and so on
04 A2 00 00 00 // Master link Video 0 for frame sync generation
04 AA 00 00 00 // Disable Vsync-Fsync overlap window
04 AB 00 00 00 // Disable Vsync-Fsync overlap window
04 A8 00 00 00 // FRM_DIFF_ERR_THR_L
04 A9 00 00 00 // FRM_DIFF_ERR_THR_H
04 A7 0c 00 00 // FSYNC_PERIOD_H, Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz
04 A6 bf 00 00 // FSYNC_PERIOD_M
04 A5 35 00 00 // FSYNC_PERIOD_L
04 AF c0 00 00 // FSYNC is GMSL2 type, use osc for fsync
04 B1 40 00 00 // FSYNC_TX_ID: set 8 to match MFP8 on serializer side
04 A0 04 00 00 // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode
];
};
};
/* serdes local device end */
/* i2c-mux start */
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser0: max96717@51 {
compatible = "maxim,ser,max96717f";
reg = <0x51>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam0: isx021@31 {
compatible = "maxim,dummy,sensor";
reg = <0x31>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser0>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam0_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser1: max96717@52 {
compatible = "maxim,ser,max96717f";
reg = <0x52>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam1: isx021@32 {
compatible = "maxim,dummy,sensor";
reg = <0x32>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser1>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam1_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser2: max96717@53 {
compatible = "maxim,ser,max96717f";
reg = <0x53>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam2: isx021@33 {
compatible = "maxim,dummy,sensor";
reg = <0x33>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser2>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam2_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser3: max96717@54 {
compatible = "maxim,ser,max96717f";
reg = <0x54>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dcphy0_cam3: isx021@34 {
compatible = "maxim,dummy,sensor";
reg = <0x34>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dcphy0_ser3>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam3_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
};
/* i2c-mux end */
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi0_in>;
};
};
};
};
&rkcif_mipi_lvds {
status = "okay";
/* parameters for do cif reset detecting:
* index0: monitor mode,
0 for idle,
1 for continue,
2 for trigger,
3 for hotplug (for nextchip)
* index1: the frame id to start timer,
min is 2
* index2: frame num of monitoring cycle
* index3: err time for keep monitoring
after finding out err (ms)
* index4: csi2 err reference val for resetting
*/
rockchip,cif-monitor = <3 2 1 1000 5>;
port {
cif_mipi0_in: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif {
status = "okay";
rockchip,android-usb-camerahal-enable;
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
max96712-dcphy0 {
max96712_dcphy0_pwdn: max96712-dcphy0-pwdn {
rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dcphy0_errb: max96712-dcphy0-errb {
rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dcphy0_lock: max96712-dcphy0-lock {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

713
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-dummy.dtsi Normal file
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@@ -0,0 +1,713 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
/ {
max96712_dphy0_osc: max96712-dphy0-oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "max96712-dphy0-osc";
};
max96712_dphy0_vcc1v2: max96712-dphy0-vcc1v2 {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy0_vcc1v2";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
startup-delay-us = <850>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dphy0_vcc1v8: max96712-dphy0-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy0_vcc1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dphy0_pwdn_regulator: max96712-dphy0-pwdn-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy0_pwdn";
gpio = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dphy0_pwdn>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
};
max96712_dphy0_poc_regulator: max96712-dphy0-poc0-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy0_poc";
gpio = <&i2c7_nca9539_gpio 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
vin-supply = <&dphy0_vcc12v_buck1>;
};
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dphy0_in_max96712: endpoint@1 {
reg = <1>;
remote-endpoint = <&max96712_dphy0_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m1_xfer>;
max96712_dphy0: max96712@29 {
compatible = "maxim4c,max96712";
status = "okay";
reg = <0x29>;
clock-names = "xvclk";
clocks = <&max96712_dphy0_osc 0>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dphy0_errb>, <&max96712_dphy0_lock>;
power-domains = <&power RK3576_PD_VI>;
rockchip,grf = <&sys_grf>;
vcc1v2-supply = <&max96712_dphy0_vcc1v2>;
vcc1v8-supply = <&max96712_dphy0_vcc1v8>;
pwdn-supply = <&max96712_dphy0_pwdn_regulator>;
lock-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
max96712_dphy0_out: endpoint {
remote-endpoint = <&mipi_dphy0_in_max96712>;
data-lanes = <1 2 3 4>;
};
};
/* support mode config start */
support-mode-config {
status = "okay";
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
sensor-width = <1920>;
sensor-height = <1440>;
max-fps-numerator = <10000>;
max-fps-denominator = <300000>;
bpp = <16>;
link-freq-idx = <20>;
};
/* support mode config end */
/* serdes local device start */
serdes-local-device {
status = "okay";
/* GMSL LINK config start */
gmsl-links {
status = "okay";
link-vdd-ldo1-en = <1>;
link-vdd-ldo2-en = <1>;
// Link A: link-id = 0
gmsl-link-config-0 {
status = "okay";
link-id = <0>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy0_cam0>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
14 D1 03 00 00 // VGAHiGain
14 45 00 00 00 // Disable SSC
];
};
};
// Link B: link-id = 1
gmsl-link-config-1 {
status = "okay";
link-id = <1>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy0_cam1>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
15 D1 03 00 00 // VGAHiGain
15 45 00 00 00 // Disable SSC
];
};
};
// Link C: link-id = 2
gmsl-link-config-2 {
status = "okay";
link-id = <2>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy0_cam2>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
16 D1 03 00 00 // VGAHiGain
16 45 00 00 00 // Disable SSC
];
};
};
// Link D: link-id = 3
gmsl-link-config-3 {
status = "okay";
link-id = <3>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy0_cam3>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
17 D1 03 00 00 // VGAHiGain
17 45 00 00 00 // Disable SSC
];
};
};
};
/* GMSL LINK config end */
/* VIDEO PIPE config start */
video-pipes {
status = "okay";
// Video Pipe 0
video-pipe-config-0 {
status = "okay";
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
];
};
};
// Video Pipe 1
video-pipe-config-1 {
status = "okay";
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
];
};
};
// Video Pipe 2
video-pipe-config-2 {
status = "okay";
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
];
};
};
// Video Pipe 3
video-pipe-config-3 {
status = "okay";
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
];
};
};
};
/* VIDEO PIPE config end */
/* MIPI TXPHY config start */
mipi-txphys {
status = "okay";
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
phy-force-clock-out = <1>; // 1: default for force clock out
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
// MIPI TXPHY A: phy-id = 0
mipi-txphy-config-0 {
status = "okay";
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0x4>;
vc-ext-en = <0>;
};
// MIPI TXPHY B: phy-id = 1
mipi-txphy-config-1 {
status = "okay";
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0xe>;
vc-ext-en = <0>;
};
};
/* MIPI TXPHY config end */
/* local device extra init sequence */
extra-init-sequence {
status = "disabled";
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// common init sequence such as fsync / gpio and so on
];
};
};
/* serdes local device end */
/* i2c-mux start */
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// Note: Serializer node defined before camera node
max96712_dphy0_ser0: max96717@51 {
compatible = "maxim,ser,max96717";
reg = <0x51>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy0_cam0: dummy@31 {
compatible = "maxim,dummy,sensor";
reg = <0x31>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy0_ser0>; // remote serializer
poc-supply = <&max96712_dphy0_poc_regulator>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy0_cam0_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// Note: Serializer node defined before camera node
max96712_dphy0_ser1: max96717@52 {
compatible = "maxim,ser,max96717";
reg = <0x52>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy0_cam1: dummy@32 {
compatible = "maxim,dummy,sensor";
reg = <0x32>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy0_ser1>; // remote serializer
poc-supply = <&max96712_dphy0_poc_regulator>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy0_cam1_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
// Note: Serializer node defined before camera node
max96712_dphy0_ser2: max96717@53 {
compatible = "maxim,ser,max96717";
reg = <0x53>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy0_cam2: dummy@33 {
compatible = "maxim,dummy,sensor";
reg = <0x33>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy0_ser2>; // remote serializer
poc-supply = <&max96712_dphy0_poc_regulator>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy0_cam2_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
// Note: Serializer node defined before camera node
max96712_dphy0_ser3: max96717@54 {
compatible = "maxim,ser,max96717";
reg = <0x54>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy0_cam3: dummy@34 {
compatible = "maxim,dummy,sensor";
reg = <0x34>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy0_ser3>; // remote serializer
poc-supply = <&max96712_dphy0_poc_regulator>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy0_cam3_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
};
/* i2c-mux end */
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi1_in>;
};
};
};
};
&rkcif_mipi_lvds1 {
status = "okay";
/* parameters for do cif reset detecting:
* index0: monitor mode,
0 for idle,
1 for continue,
2 for trigger,
3 for hotplug (for nextchip)
* index1: the frame id to start timer,
min is 2
* index2: frame num of monitoring cycle
* index3: err time for keep monitoring
after finding out err (ms)
* index4: csi2 err reference val for resetting
*/
rockchip,cif-monitor = <3 2 1 1000 5>;
port {
cif_mipi1_in: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
};
};
};
&rkcif {
status = "okay";
rockchip,android-usb-camerahal-enable;
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
max96712-dphy0 {
max96712_dphy0_pwdn: max96712-dphy0-pwdn {
rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy0_errb: max96712-dphy0-errb {
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy0_lock: max96712-dphy0-lock {
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

713
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy3-dummy.dtsi Normal file
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@@ -0,0 +1,713 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
/ {
max96712_dphy3_osc: max96712-dphy3-oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "max96712-dphy3-osc";
};
max96712_dphy3_vcc1v2: max96712-dphy3-vcc1v2 {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_vcc1v2";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
startup-delay-us = <850>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dphy3_vcc1v8: max96712-dphy3-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_vcc1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dphy3_pwdn_regulator: max96712-dphy3-pwdn-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_pwdn";
gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dphy3_pwdn>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
};
max96712_dphy3_poc_regulator: max96712-dphy3-poc-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_poc";
gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
vin-supply = <&dphy3_vcc12v_buck1>;
};
};
&csi2_dphy1_hw {
status = "okay";
};
&csi2_dphy3 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dphy3_in_max96712: endpoint@1 {
reg = <1>;
remote-endpoint = <&max96712_dphy3_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy3_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&i2c8 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c8m2_xfer>;
max96712_dphy3: max96712@29 {
compatible = "maxim4c,max96712";
status = "okay";
reg = <0x29>;
clock-names = "xvclk";
clocks = <&max96712_dphy3_osc 0>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dphy3_errb>, <&max96712_dphy3_lock>;
power-domains = <&power RK3576_PD_VI>;
rockchip,grf = <&sys_grf>;
vcc1v2-supply = <&max96712_dphy3_vcc1v2>;
vcc1v8-supply = <&max96712_dphy3_vcc1v8>;
pwdn-supply = <&max96712_dphy3_pwdn_regulator>;
lock-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
max96712_dphy3_out: endpoint {
remote-endpoint = <&mipi_dphy3_in_max96712>;
data-lanes = <1 2 3 4>;
};
};
/* support mode config start */
support-mode-config {
status = "okay";
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
sensor-width = <1920>;
sensor-height = <1440>;
max-fps-numerator = <10000>;
max-fps-denominator = <300000>;
bpp = <16>;
link-freq-idx = <20>;
};
/* support mode config end */
/* serdes local device start */
serdes-local-device {
status = "okay";
/* GMSL LINK config start */
gmsl-links {
status = "okay";
link-vdd-ldo1-en = <1>;
link-vdd-ldo2-en = <1>;
// Link A: link-id = 0
gmsl-link-config-0 {
status = "okay";
link-id = <0>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam0>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
14 D1 03 00 00 // VGAHiGain
14 45 00 00 00 // Disable SSC
];
};
};
// Link B: link-id = 1
gmsl-link-config-1 {
status = "okay";
link-id = <1>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam1>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
15 D1 03 00 00 // VGAHiGain
15 45 00 00 00 // Disable SSC
];
};
};
// Link C: link-id = 2
gmsl-link-config-2 {
status = "okay";
link-id = <2>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam2>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
16 D1 03 00 00 // VGAHiGain
16 45 00 00 00 // Disable SSC
];
};
};
// Link D: link-id = 3
gmsl-link-config-3 {
status = "okay";
link-id = <3>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam3>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
17 D1 03 00 00 // VGAHiGain
17 45 00 00 00 // Disable SSC
];
};
};
};
/* GMSL LINK config end */
/* VIDEO PIPE config start */
video-pipes {
status = "okay";
// Video Pipe 0
video-pipe-config-0 {
status = "okay";
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
];
};
};
// Video Pipe 1
video-pipe-config-1 {
status = "okay";
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
];
};
};
// Video Pipe 2
video-pipe-config-2 {
status = "okay";
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
];
};
};
// Video Pipe 3
video-pipe-config-3 {
status = "okay";
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
];
};
};
};
/* VIDEO PIPE config end */
/* MIPI TXPHY config start */
mipi-txphys {
status = "okay";
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
phy-force-clock-out = <1>; // 1: default for force clock out
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
// MIPI TXPHY A: phy-id = 0
mipi-txphy-config-0 {
status = "okay";
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0x4>;
vc-ext-en = <0>;
};
// MIPI TXPHY B: phy-id = 1
mipi-txphy-config-1 {
status = "okay";
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0xe>;
vc-ext-en = <0>;
};
};
/* MIPI TXPHY config end */
/* local device extra init sequence */
extra-init-sequence {
status = "disabled";
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// common init sequence such as fsync / gpio and so on
];
};
};
/* serdes local device end */
/* i2c-mux start */
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser0: max96717@51 {
compatible = "maxim,ser,max96717";
reg = <0x51>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam0: dummy@31 {
compatible = "maxim,dummy,sensor";
reg = <0x31>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser0>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam0_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser1: max96717@52 {
compatible = "maxim,ser,max96717";
reg = <0x52>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam1: dummy@32 {
compatible = "maxim,dummy,sensor";
reg = <0x32>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser1>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam1_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser2: max96717@53 {
compatible = "maxim,ser,max96717";
reg = <0x53>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam2: dummy@33 {
compatible = "maxim,dummy,sensor";
reg = <0x33>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser2>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam2_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser3: max96717@54 {
compatible = "maxim,ser,max96717";
reg = <0x54>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam3: dummy@34 {
compatible = "maxim,dummy,sensor";
reg = <0x34>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser3>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam3_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
};
/* i2c-mux end */
};
};
&mipi3_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy3_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi3_in>;
};
};
};
};
&rkcif_mipi_lvds3 {
status = "okay";
/* parameters for do cif reset detecting:
* index0: monitor mode,
0 for idle,
1 for continue,
2 for trigger,
3 for hotplug (for nextchip)
* index1: the frame id to start timer,
min is 2
* index2: frame num of monitoring cycle
* index3: err time for keep monitoring
after finding out err (ms)
* index4: csi2 err reference val for resetting
*/
rockchip,cif-monitor = <3 2 1 1000 5>;
port {
cif_mipi3_in: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif {
status = "okay";
rockchip,android-usb-camerahal-enable;
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
max96712-dphy3 {
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy3_errb: max96712-dphy3-errb {
rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy3_lock: max96712-dphy3-lock {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

725
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy3-isx021.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
/ {
max96712_dphy3_osc: max96712-dphy3-oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "max96712-dphy3-osc";
};
max96712_dphy3_vcc1v2: max96712-dphy3-vcc1v2 {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_vcc1v2";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
startup-delay-us = <850>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dphy3_vcc1v8: max96712-dphy3-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_vcc1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dphy3_pwdn_regulator: max96712-dphy3-pwdn-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_pwdn";
gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dphy3_pwdn>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
};
max96712_dphy3_poc_regulator: max96712-dphy3-poc-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dphy3_poc";
gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
vin-supply = <&dphy3_vcc12v_buck1>;
};
};
&csi2_dphy1_hw {
status = "okay";
};
&csi2_dphy3 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dphy3_in_max96712: endpoint@1 {
reg = <1>;
remote-endpoint = <&max96712_dphy3_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy3_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&i2c8 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c8m2_xfer>;
max96712_dphy3: max96712@29 {
compatible = "maxim4c,max96712";
status = "okay";
reg = <0x29>;
clock-names = "xvclk";
clocks = <&max96712_dphy3_osc 0>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dphy3_errb>, <&max96712_dphy3_lock>;
power-domains = <&power RK3576_PD_VI>;
rockchip,grf = <&sys_grf>;
vcc1v2-supply = <&max96712_dphy3_vcc1v2>;
vcc1v8-supply = <&max96712_dphy3_vcc1v8>;
pwdn-supply = <&max96712_dphy3_pwdn_regulator>;
lock-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
max96712_dphy3_out: endpoint {
remote-endpoint = <&mipi_dphy3_in_max96712>;
data-lanes = <1 2 3 4>;
};
};
/* support mode config start */
support-mode-config {
status = "okay";
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
sensor-width = <1920>;
sensor-height = <1281>;
crop-rect = <0 1 1920 1280>; // [ left, top, width, height ]
max-fps-numerator = <10000>;
max-fps-denominator = <300000>;
bpp = <16>;
link-freq-idx = <20>;
};
/* support mode config end */
/* serdes local device start */
serdes-local-device {
status = "okay";
/* GMSL LINK config start */
gmsl-links {
status = "okay";
link-vdd-ldo1-en = <1>;
link-vdd-ldo2-en = <1>;
// Link A: link-id = 0
gmsl-link-config-0 {
status = "okay";
link-id = <0>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam0>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
14 D1 03 00 00 // VGAHiGain
14 45 00 00 00 // Disable SSC
];
};
};
// Link B: link-id = 1
gmsl-link-config-1 {
status = "okay";
link-id = <1>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam1>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
15 D1 03 00 00 // VGAHiGain
15 45 00 00 00 // Disable SSC
];
};
};
// Link C: link-id = 2
gmsl-link-config-2 {
status = "okay";
link-id = <2>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam2>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
16 D1 03 00 00 // VGAHiGain
16 45 00 00 00 // Disable SSC
];
};
};
// Link D: link-id = 3
gmsl-link-config-3 {
status = "okay";
link-id = <3>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dphy3_cam3>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
17 D1 03 00 00 // VGAHiGain
17 45 00 00 00 // Disable SSC
];
};
};
};
/* GMSL LINK config end */
/* VIDEO PIPE config start */
video-pipes {
status = "okay";
// Video Pipe 0
video-pipe-config-0 {
status = "okay";
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
];
};
};
// Video Pipe 1
video-pipe-config-1 {
status = "okay";
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
];
};
};
// Video Pipe 2
video-pipe-config-2 {
status = "okay";
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
];
};
};
// Video Pipe 3
video-pipe-config-3 {
status = "okay";
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
];
};
};
};
/* VIDEO PIPE config end */
/* MIPI TXPHY config start */
mipi-txphys {
status = "okay";
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
phy-force-clock-out = <1>; // 1: default for force clock out
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
// MIPI TXPHY A: phy-id = 0
mipi-txphy-config-0 {
status = "okay";
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0x4>;
vc-ext-en = <0>;
};
// MIPI TXPHY B: phy-id = 1
mipi-txphy-config-1 {
status = "okay";
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0xe>;
vc-ext-en = <0>;
};
};
/* MIPI TXPHY config end */
/* local device extra init sequence */
extra-init-sequence {
status = "okay";
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// common init sequence such as fsync / gpio and so on
04 A2 00 00 00 // Master link Video 0 for frame sync generation
04 AA 00 00 00 // Disable Vsync-Fsync overlap window
04 AB 00 00 00 // Disable Vsync-Fsync overlap window
04 A8 00 00 00 // FRM_DIFF_ERR_THR_L
04 A9 00 00 00 // FRM_DIFF_ERR_THR_H
04 A7 0c 00 00 // FSYNC_PERIOD_H, Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz
04 A6 bf 00 00 // FSYNC_PERIOD_M
04 A5 35 00 00 // FSYNC_PERIOD_L
04 AF c0 00 00 // FSYNC is GMSL2 type, use osc for fsync
04 B1 40 00 00 // FSYNC_TX_ID: set 8 to match MFP8 on serializer side
04 A0 04 00 00 // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode
];
};
};
/* serdes local device end */
/* i2c-mux start */
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser0: max96717@51 {
compatible = "maxim,ser,max96717f";
reg = <0x51>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam0: isx021@31 {
compatible = "maxim,dummy,sensor";
reg = <0x31>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser0>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam0_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser1: max96717@52 {
compatible = "maxim,ser,max96717f";
reg = <0x52>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam1: isx021@32 {
compatible = "maxim,dummy,sensor";
reg = <0x32>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser1>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam1_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser2: max96717@53 {
compatible = "maxim,ser,max96717f";
reg = <0x53>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam2: isx021@33 {
compatible = "maxim,dummy,sensor";
reg = <0x33>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser2>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam2_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
// Note: Serializer node defined before camera node
max96712_dphy3_ser3: max96717@54 {
compatible = "maxim,ser,max96717f";
reg = <0x54>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
03 02 10 00 00
14 17 00 00 00
14 32 7f 00 00
];
};
};
max96712_dphy3_cam3: isx021@34 {
compatible = "maxim,dummy,sensor";
reg = <0x34>;
cam-i2c-addr-def = <0x30>;
cam-remote-ser = <&max96712_dphy3_ser3>; // remote serializer
poc-supply = <&max96712_dphy3_poc_regulator>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dphy3_cam3_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
};
/* i2c-mux end */
};
};
&mipi3_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy3_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi3_in>;
};
};
};
};
&rkcif_mipi_lvds3 {
status = "okay";
/* parameters for do cif reset detecting:
* index0: monitor mode,
0 for idle,
1 for continue,
2 for trigger,
3 for hotplug (for nextchip)
* index1: the frame id to start timer,
min is 2
* index2: frame num of monitoring cycle
* index3: err time for keep monitoring
after finding out err (ms)
* index4: csi2 err reference val for resetting
*/
rockchip,cif-monitor = <3 2 1 1000 5>;
port {
cif_mipi3_in: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif {
status = "okay";
rockchip,android-usb-camerahal-enable;
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
max96712-dphy3 {
max96712_dphy3_pwdn: max96712-dphy3-pwdn {
rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dphy3_errb: max96712-dphy3-errb {
rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dphy3_lock: max96712-dphy3-lock {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};