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serial: 8250: set fifo rx trigger 1/2 of fifo

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To reduce the uart interrupts, which may cause:

serial8250: too much work for irq xx

Change-Id: I89e0d990677e4cffae431e60521b3e16e8381f05
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
This commit is contained in:
Huibin Hong
2018-05-08 15:46:30 +08:00
committed by Tao Huang
parent f18548643d
commit 2003c94bc0
1 changed files with 3 additions and 1 deletions
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4
drivers/tty/serial/8250/8250_port.c
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@@ -2748,7 +2748,9 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
}
serial8250_set_divisor(port, baud, quot, frac);
#ifdef CONFIG_ARCH_ROCKCHIP
up->fcr = UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_10 | UART_FCR_R_TRIG_10;
#endif
/*
* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
* is written without DLAB set, this mode will be disabled.