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deinterlace: change holdline default value to 8 [1/1]
PD#SWPL-3384 Problem: DI post holdline setting is not map with video Solution: change holdline to 8 Verify: verified by gxl Change-Id: Ia352604086cefb4c69d5dd268d12741c4cf4f173 Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
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@@ -263,7 +263,7 @@ static long same_field_bot_count;
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* 1, keep 4 buffers in pre_ready_list for checking;
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*/
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static int post_hold_line = 17;/* for m8 1080i/50 output */
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static int post_hold_line = 8; /*2019-01-10: from VLSI feijun from 17 to 8*/
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static int post_urgent = 1;
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/*pre process speed debug */
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@@ -7405,6 +7405,7 @@ static void set_di_flag(void)
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post_hold_line =
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(is_meson_g12a_cpu() || is_meson_g12b_cpu())?10:17;
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} else {
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post_hold_line = 8; /*2019-01-10: from VLSI feijun*/
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mcpre_en = false;
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pulldown_enable = false;
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di_pre_rdma_enable = false;
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