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clk: rockchip: px30: Add SCLK_DDRCLK for dmc

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Change-Id: I03d6c18829f8895c28bbaef883e187304c48f9aa
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
YouMin Chen
2018-02-05 10:54:50 +08:00
committed by Tao Huang
parent 7d93bcf246
commit 24d2386997
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/rockchip/clk-px30.c
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@@ -326,8 +326,9 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
PX30_CLKGATE_CON(0), 7, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p,
CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, 0, 3,
ROCKCHIP_DDRCLK_SIP_V2),
COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,