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clk: rockchip: rv1106: optimize calibrate step for cru pvtpll

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The frequency of pvtpll may unstable when calibrate, if the step
is too small, it will stride a too big length and adjust back
again, that is bad.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I96227b37cde45ae86df68777da8f32467f8926e6
This commit is contained in:
Liang Chen
2024-02-20 15:14:57 +08:00
committed by Chen Liang
parent f3fcf22888
commit 25c456719d
1 changed files with 6 additions and 2 deletions
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8
drivers/clk/rockchip/clk-rv1106.c
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@@ -1007,12 +1007,16 @@ static void _cru_pvtpll_calibrate(int count_offset, int length_offset, int targe
writel_relaxed(val, rv1106_cru_base + length_offset);
usleep_range(2000, 2100);
rate1 = readl_relaxed(rv1106_cru_base + count_offset);
if ((rate1 < target_rate) || (rate1 >= rate0))
if (rate1 < target_rate)
return;
if (abs(rate1 - target_rate) < (target_rate >> 5))
return;
step = rate0 - rate1;
if (rate1 < rate0)
step = rate0 - rate1;
else
step = 5;
step = max_t(unsigned int, step, 5);
delta = rate1 - target_rate;
length += delta / step;
val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);