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phy: rockchip: naneng-combphy: update to use T3 for PCIe TRIM

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According to HW signal test, the T3 parameter is the best setting for
non-SSC mode, need to co-work with PPLL and DIV PF10.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I3b701f714bd63e08bb5d47046c37bba6701c4f8a
This commit is contained in:
Kever Yang
2022-04-19 11:52:01 +08:00
parent 94f439584b
commit 2accc53726
1 changed files with 5 additions and 3 deletions
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8
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -762,11 +762,13 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
val = 0x4c;
writel(val, priv->mmio + (0x1b << 2));
/* Set up su_trim: */
val = 0xf0;
/* Set up su_trim: T3 */
val = 0xb0;
writel(val, priv->mmio + (0xa << 2));
val = 0x4;
val = 0x47;
writel(val, priv->mmio + (0xb << 2));
val = 0x57;
writel(val, priv->mmio + (0xd << 2));
} else if (priv->mode == PHY_TYPE_SATA) {
/* downward spread spectrum +500ppm */
val = readl(priv->mmio + (0x1f << 2));