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clk: rockchip: rv1126: mux clocks to none-cpll/hpll

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There is a lower power dissipation requirement for some products, like
battery ipc, bell, etc... We have to gate cpll/hpll to reduce power
dissipation.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I48fae621c980b6f7f7d8e8ca71171febd6c6a9a8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2020-09-28 19:48:50 +08:00
committed by Tao Huang
parent f44db7e0f1
commit 2aed1b5b93
1 changed files with 4 additions and 0 deletions
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4
drivers/clk/rockchip/clk-pll.c
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@@ -1252,8 +1252,12 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
/* now create the actual pll */
init.name = pll_name;
#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
/* keep all plls untouched for now */
init.flags = flags | CLK_IGNORE_UNUSED;
#else
init.flags = flags;
#endif
init.parent_names = &parent_names[0];
init.num_parents = 1;